{"id":56073,"date":"2020-02-04T00:00:00","date_gmt":"2020-02-03T21:00:00","guid":{"rendered":"https:\/\/prohoster.info\/blog\/blog_prohoster\/neizbezhnost-proniknoveniya-fpga-v-data-tsentry"},"modified":"2020-02-18T14:04:16","modified_gmt":"2020-02-18T11:04:16","slug":"neizbezhnost-proniknoveniya-fpga-v-data-tsentry","status":"publish","type":"post","link":"https:\/\/prohoster.info\/az\/blog\/administrirovanie\/neizbezhnost-proniknoveniya-fpga-v-data-tsentry","title":{"rendered":"FPGA-n\u0131n data m\u0259rk\u0259zl\u0259rin\u0259 daxil olmas\u0131n\u0131n qa\u00e7\u0131lmazl\u0131\u011f\u0131","gt_translate_keys":[{"key":"rendered","format":"text"}]},"content":{"rendered":"

\"FPGA-n\u0131n
\nFPGA \u00fc\u00e7\u00fcn proqram yazmaq \u00fc\u00e7\u00fcn \u00e7ip istehsal\u00e7\u0131s\u0131 olma\u011fa ehtiyac yoxdur, Java-dan kod yazmaq \u00fc\u00e7\u00fcn is\u0259 proqram\u00e7\u0131 olma\u011fa ehtiyac yoxdur. Ancaq h\u0259r iki halda, bu bacar\u0131qlar\u0131n olmas\u0131 m\u00fctl\u0259q faydal\u0131d\u0131r.<\/p>\n

Java v\u0259 FPGA-n\u0131n kommersiyala\u015fd\u0131r\u0131lmas\u0131 m\u0259qs\u0259di sonuncu b\u0259yanat\u0131 t\u0259kzib etm\u0259kdir. FPGA \u00fc\u00e7\u00fcn yax\u015f\u0131 x\u0259b\u0259r budur ki, uy\u011fun abstraksiya v\u0259 al\u0259t d\u0259stl\u0259ri il\u0259, proqramlanabil\u0259n loqika cihaz\u0131 icad edildiyind\u0259n b\u0259ri, son 35 il \u0259rzind\u0259 FPGA \u00fc\u00e7\u00fcn algoritml\u0259r v\u0259 m\u0259lumat ax\u0131nlar\u0131 yaratmaq, CPU, DSP, GPU v\u0259 ya dig\u0259r x\u00fcsusi ASIC-l\u0259r \u0259v\u0259zin\u0259 daha da asanla\u015f\u0131r.<\/p>\n

Onlar\u0131n yarad\u0131lmas\u0131n\u0131n m\u00f6c\u00fcz\u0259vi vaxt\u0131nda, CPU-lar\u0131n art\u0131q t\u0259k hesablama modulu kimi qalmas\u0131na ehtiyac yox idi data m\u0259rk\u0259zl\u0259ri infrastrukturundan istifad\u0259 edirik.<\/a> m\u00fcxt\u0259lif s\u0259b\u0259bl\u0259rd\u0259n \u2013 FPGA \u00f6z effektivliyin\u0259 \u00e7atd\u0131, s\u00fcr\u0259t, gecikm\u0259, \u015f\u0259b\u0259k\u0259 imkanlar\u0131 v\u0259 yadda\u015f t\u0259qdim etdi \u2013 m\u00fcasir FPGA SoC-l\u0259rin heterojen hesablamal\u0131 imkanlar\u0131, dem\u0259k olar ki, tam hesablamal\u0131 sisteml\u0259r t\u0259\u015fkil edir. Ancaq FPGA dig\u0259r cihazlarla da u\u011furla inteqrasiya edilir v\u0259 bizim fikrimizc\u0259, bu sisteml\u0259r yaln\u0131z hesablamalar ierarxiyas\u0131nda \u00f6z qanuni yerini tapma\u011fa ba\u015flay\u0131r.
\n<\/a><\/noindex>
\nBuna g\u00f6r\u0259 d\u0259, 22 yanvar tarixind\u0259 San-Hose \u015f\u0259h\u0259rind\u0259 The Next FPGA Platform konfrans\u0131 t\u0259\u015fkil etdik. T\u0259biidir ki, d\u00fcnyada FPGA-lar\u0131n \u0259sas t\u0259minat\u00e7\u0131lar\u0131ndan biri v\u0259 bu sah\u0259d\u0259 pionerdir Xilinx. Xilinx-in ba\u015f vitse-prezidenti v\u0259 texniki direktoru Ivo Bolsens konfransda \u00e7\u0131x\u0131\u015f etdi v\u0259 biz\u0259 Xilinx-in data m\u0259rk\u0259zl\u0259ri \u00fc\u00e7\u00fcn d\u0259yi\u015f\u0259n hesablama sisteml\u0259ri yaratma\u011fa nec\u0259 k\u00f6m\u0259k etdiyin\u0259 dair g\u00fcn\u00fcm\u00fczd\u0259ki d\u00fc\u015f\u00fcnc\u0259l\u0259ri haqq\u0131nda m\u0259lumat verdi.<\/p>\n

Sistem memarlar\u0131 v\u0259 proqram\u00e7\u0131lar\u0131n\u0131n m\u00fcxt\u0259lif n\u00f6v hesablama qabiliyy\u0259tl\u0259rinin n\u00fcmayi\u015f etdirildiyi qeyri-homogen data m\u0259rk\u0259zin\u0259 g\u0259lm\u0259k \u00fc\u00e7\u00fcn kifay\u0259t q\u0259d\u0259r vaxt\u0131 ke\u00e7di, bu, hesablamalar, m\u0259lumat saxlanmas\u0131 v\u0259 \u015f\u0259b\u0259k\u0259l\u0259r t\u0259\u015fkil etm\u0259k m\u0259s\u0259l\u0259l\u0259rini h\u0259ll edir. Bunun, m\u00fcxt\u0259lif CMOS-lar istifad\u0259 etm\u0259kl\u0259 Moore qanununa uy\u011fun g\u0259lm\u0259k \u00e7\u0259tinl\u0259\u015fdiyind\u0259n vacib oldu\u011fu g\u00f6r\u00fcn\u00fcr. H\u0259l\u0259 d\u0259 dilimiz CPU-lara ba\u011fl\u0131d\u0131r v\u0259 h\u0259l\u0259 d\u0259 \"t\u0259tbiql\u0259rin s\u00fcr\u0259tl\u0259ndirilm\u0259si\" il\u0259 \u0259laq\u0259dar dan\u0131\u015f\u0131r\u0131q, yaln\u0131z CPU-lar \u00fcz\u0259rind\u0259 n\u0259 ed\u0259 bil\u0259c\u0259yimizl\u0259 m\u00fcqayis\u0259d\u0259 proqramlar\u0131n i\u015fini yax\u015f\u0131la\u015fd\u0131rma\u011fa i\u015far\u0259 edirik. Bir az sonra data m\u0259rk\u0259zl\u0259ri, hesablama g\u00fccl\u0259ri, m\u0259lumat saxlanmas\u0131 v\u0259 h\u0259r \u015feyi bir araya g\u0259tir\u0259n protokollar toplusuna \u00e7evril\u0259c\u0259k v\u0259 \"hesablamalar\" v\u0259 \"t\u0259tbiql\u0259r\" kimi terminl\u0259r\u0259 qay\u0131daca\u011f\u0131q. Hibrid hesablama, bug\u00fcnk\u00fc standart \"bulud\" xidm\u0259tl\u0259ri kimi normaya \u00e7evril\u0259c\u0259k. virtual ma\u015f\u0131nlar<\/a>, v\u0259 bir m\u00fcdd\u0259t sonra onlar\u0131n i\u015fini t\u0259svir etm\u0259k \u00fc\u00e7\u00fcn sad\u0259c\u0259 \u00abhesablama\u00bb s\u00f6z\u00fcn\u00fc istifad\u0259 ed\u0259c\u0259yik. Bir m\u00fcdd\u0259t sonra - v\u0259 bu d\u00f6vr\u00fcn yaranmas\u0131na FPGA-lar aktiv \u015f\u0259kild\u0259 k\u00f6m\u0259k ed\u0259c\u0259k - biz bunu yenid\u0259n m\u0259lumatlar\u0131n i\u015fl\u0259nm\u0259si adland\u0131raca\u011f\u0131q.<\/p>\n

FPGA-n\u0131n m\u0259lumat m\u0259rk\u0259zl\u0259rin\u0259 daxil edilm\u0259si \u00fc\u00e7\u00fcn d\u00fc\u015f\u00fcnc\u0259 t\u0259rzinin d\u0259yi\u015fdirilm\u0259si t\u0259l\u0259b olunur. \u00abBug\u00fcnk\u00fc proqramlar\u0131 s\u00fcr\u0259tl\u0259ndirm\u0259k yollar\u0131n\u0131 d\u00fc\u015f\u00fcnd\u00fckd\u0259, onlar\u0131n icra olunma prinsipl\u0259rinin, istifad\u0259 olunan resurslar\u0131n v\u0259 vaxt\u0131n haraya getdiyinin d\u0259rinlikl\u0259rin\u0259 enm\u0259k laz\u0131md\u0131r\u00bb - izah edir Bolsens. - \u00abH\u0259d\u0259fl\u0259diyiniz \u00fcmumi probleml\u0259ri \u00f6yr\u0259nm\u0259k vacibdir. Hal-haz\u0131rda m\u0259lumat m\u0259rk\u0259zl\u0259rind\u0259 i\u015fl\u0259y\u0259n bir \u00e7ox t\u0259tbiq geni\u015fl\u0259nir, b\u00f6y\u00fck resurslar\u0131 \u0259hat\u0259 edir. M\u0259s\u0259l\u0259n, ma\u015f\u0131n \u00f6yr\u0259nm\u0259si, \u00e7ox sayda hesablama d\u00fcy\u00fcnl\u0259ri istifad\u0259 edir. Ancaq s\u00fcr\u0259tl\u0259nm\u0259d\u0259n dan\u0131\u015fark\u0259n yaln\u0131z hesablamalar\u0131n s\u00fcr\u0259tini d\u00fc\u015f\u00fcnm\u0259k kifay\u0259t etmir, eyni zamanda infrastrukturu s\u00fcr\u0259tl\u0259ndirm\u0259k d\u0259 laz\u0131md\u0131r.\u00bb<\/p>\n

M\u0259s\u0259l\u0259n, Bolsensin praktiki olaraq \u00f6yr\u0259ndiyi ma\u015f\u0131n \u00f6yr\u0259nm\u0259si il\u0259 ba\u011fl\u0131 \u0259m\u0259liyyatlarda vaxt\u0131n t\u0259xmin\u0259n 50%-i, yay\u0131lm\u0131\u015f hesablama g\u00fccl\u0259ri aras\u0131nda m\u0259lumatlar\u0131 yuxar\u0131 v\u0259 a\u015fa\u011f\u0131 \u00f6t\u00fcrm\u0259y\u0259 s\u0259rf edilir, yaln\u0131z qalan yar\u0131 (50%) vaxt is\u0259 \u00f6z\u00fc hesablama i\u015fl\u0259rin\u0259 s\u0259rf olunur.<\/p>\n

\u00abM\u0259nc\u0259, burada FPGA k\u00f6m\u0259k ed\u0259 bil\u0259r, \u00e7\u00fcnki biz t\u0259tbiqin h\u0259m hesablama, h\u0259m d\u0259 m\u0259lumatlar\u0131n \u00f6t\u00fcr\u00fclm\u0259si aspektl\u0259rini optimalla\u015fd\u0131rma\u011f\u0131 t\u0259min ed\u0259 bil\u0259rik. V\u0259 bunu \u00fcmumi infrastruktur s\u0259viyy\u0259sind\u0259, h\u0259m d\u0259 \u00e7ip s\u0259viyy\u0259sind\u0259 ed\u0259 bil\u0259rik. Bu, FPGA-n\u0131n \u0259n b\u00f6y\u00fck \u00fcst\u00fcnl\u00fckl\u0259rind\u0259n biridir; x\u00fcsusi t\u0259tbiql\u0259rin t\u0259l\u0259bl\u0259rin\u0259 uy\u011fun olaraq kommunikasiyalar\u0131n \u015f\u0259b\u0259k\u0259l\u0259rini yaratma\u011fa imkan verir. S\u00fcni intellekt il\u0259 ba\u011fl\u0131 probleml\u0259rd\u0259 m\u0259lumatlar\u0131n \u00f6t\u00fcr\u00fclm\u0259si \u00fc\u00e7\u00fcn tipik nax\u0131\u015flara baxanda, m\u0259n m\u00fcr\u0259kk\u0259b kommutator \u0259sasl\u0131 arxitekturan\u0131n z\u0259ruriliyi g\u00f6rm\u00fcr\u0259m. B\u00f6y\u00fck veril\u0259n ax\u0131n\u0131 il\u0259 bir \u015f\u0259b\u0259k\u0259 qurmaq m\u00fcmk\u00fcnd\u00fcr. Eyni \u015fey neyron \u015f\u0259b\u0259k\u0259l\u0259rinin \u00f6yr\u0259nilm\u0259si il\u0259 ba\u011fl\u0131 m\u0259s\u0259l\u0259l\u0259r\u0259 d\u0259 aiddir - x\u00fcsusi probleml\u0259r\u0259 uy\u011fun \u00f6l\u00e7\u00fcl\u00fc paketl\u0259rl\u0259 h\u00fcceyr\u0259vi bir \u015f\u0259b\u0259k\u0259 qurmaq m\u00fcmk\u00fcnd\u00fcr. FPGA istifad\u0259 ed\u0259r\u0259k m\u0259lumatlar\u0131n \u00f6t\u00fcr\u00fclm\u0259si protokollar\u0131n\u0131 v\u0259 sxem topologiyas\u0131n\u0131 konkret t\u0259tbiq \u00fc\u00e7\u00fcn \u00e7ox d\u0259qiq \u015f\u0259kild\u0259 \u00f6l\u00e7m\u0259k v\u0259 uy\u011funla\u015fd\u0131rmaq m\u00fcmk\u00fcnd\u00fcr. V\u0259 ma\u015f\u0131n \u00f6yr\u0259nm\u0259si il\u0259 ba\u011fl\u0131, eyni zamanda, biz\u0259 ikili d\u0259qiqlikd\u0259 onluq \u0259d\u0259dl\u0259r laz\u0131m olmad\u0131\u011f\u0131n\u0131 da ayd\u0131nl\u0131qla bildiyimiz \u00fc\u00e7\u00fcn bunu da uy\u011funla\u015fd\u0131ra bil\u0259rik.\u00bb<\/p>\n

FPGA il\u0259 CPU v\u0259 ya spesifik ASIC aras\u0131ndak\u0131 f\u0259rq ondan ibar\u0259tdir ki, sonuncular istehsal zaman\u0131 proqramla\u015fd\u0131r\u0131l\u0131r v\u0259 bundan sonra hesablama veril\u0259nl\u0259ri v\u0259 ya elementl\u0259rinin n\u00f6vl\u0259ri, ya da cihazdan ke\u00e7\u0259n m\u0259lumat ax\u0131n\u0131n\u0131n t\u0259bi\u0259ti haqq\u0131nda d\u00fc\u015f\u00fcnm\u0259k m\u00fcmk\u00fcn olmur. FPGA-lar siz\u0259 i\u015f \u015f\u0259raiti d\u0259yi\u015f\u0259rs\u0259 yenid\u0259n d\u00fc\u015f\u00fcnm\u0259k imkan\u0131 verir.<\/p>\n

\u018fvv\u0259ll\u0259r bu \u00fcst\u00fcnl\u00fck baha ba\u015fa g\u0259lirdi, \u00e7\u00fcnki FPGA \u00fc\u00e7\u00fcn proqramla\u015fd\u0131rma z\u0259if ruhlu insanlar \u00fc\u00e7\u00fcn n\u0259z\u0259rd\u0259 tutulmam\u0131\u015fd\u0131. FPGA kompilatorlar\u0131n\u0131 a\u00e7maq t\u0259l\u0259b olunur ki, onlar CPU \u00fc\u00e7\u00fcn paralel hesablamalar yaratmaq \u00fc\u00e7\u00fcn proqram\u00e7\u0131lar t\u0259r\u0259find\u0259n istifad\u0259 olunan al\u0259tl\u0259rl\u0259 daha yax\u015f\u0131 inteqrasiya olusun, v\u0259 FPGA-da prosesl\u0259ri s\u00fcr\u0259tl\u0259ndirm\u0259k \u00fc\u00e7\u00fcn kitabxanalara bir hiss\u0259 i\u015f verilsin. Bununla yana\u015f\u0131, Vitis ma\u015f\u0131n \u00f6yr\u0259nm\u0259 st\u0259kinin m\u0259rk\u0259zind\u0259dir, Caffe v\u0259 TensorFlow kimi MO platformalar\u0131n\u0131n \u0259sas\u0131n\u0131 t\u0259\u015fkil edir v\u0259 adi AI modell\u0259rini i\u015f\u0259 salmaq v\u0259 ya b\u0259nz\u0259r tap\u015f\u0131r\u0131qlara, m\u0259s\u0259l\u0259n, video kodla\u015fd\u0131rma, videoda obyektl\u0259rin tan\u0131nmas\u0131, m\u0259lumat analizi, maliyy\u0259 riskl\u0259rinin idar\u0259 edilm\u0259si v\u0259 h\u0259r hans\u0131 \u00fc\u00e7\u00fcnc\u00fc t\u0259r\u0259f kitabxanalar\u0131na FPGA imkanlar\u0131n\u0131 \u0259lav\u0259 etm\u0259k \u00fc\u00e7\u00fcn kitabxanalara malikdir.<\/p>\n

Bu konsepsiya Nvidia-n\u0131n 10 il \u0259vv\u0259l ba\u015flad\u0131lan CUDA layih\u0259sind\u0259n v\u0259 paralel hesablamalar\u0131 GPU s\u00fcr\u0259tl\u0259ndiricil\u0259rin\u0259 k\u00f6\u00e7\u00fcr\u0259n layih\u0259sind\u0259n, el\u0259c\u0259 d\u0259 AMD-nin ROCm al\u0259tl\u0259r d\u0259stind\u0259n v\u0259 Intel-in OneAPI layih\u0259sinin, m\u00fcxt\u0259lif CPU, GPU v\u0259 FPGA-larda i\u015fl\u0259m\u0259li oldu\u011fu v\u0259dl\u0259rind\u0259n \u00e7ox da f\u0259rql\u0259nmir.<\/p>\n

Suala yaln\u0131z bunlar\u0131n nec\u0259 birl\u0259\u015fdiril\u0259c\u0259yi aiddir ki, h\u0259r k\u0259s \u00f6z se\u00e7imi il\u0259 hesablam\u0259 g\u00fcc\u00fc d\u0259stini proqramla\u015fd\u0131ra bilsin. Bu vacibdir, \u00e7\u00fcnki FPGA-lar \u0259vv\u0259lki CPU-lardan daha m\u00fcr\u0259kk\u0259b olub. Onlar \u0259n qabaqc\u0131l istehsal prosesl\u0259ri il\u0259 v\u0259 \u0259n m\u00fcasir \u00e7ip qabla\u015fd\u0131rma texnologiyalar\u0131 il\u0259 istehsal olunur. V\u0259 onlar m\u00fctl\u0259q \u00f6z ni\u015fl\u0259rini tapacaqlar, \u00e7\u00fcnki art\u0131q vaxt, pul, enerji v\u0259 intellekti bo\u015funa s\u0259rf etm\u0259y\u0259 imkan\u0131m\u0131z qalmay\u0131b \u2013 bunlar \u00e7ox bahal\u0131 resurslard\u0131r.<\/p>\n

\u00abFPGA texnoloji \u00fcst\u00fcnl\u00fckl\u0259r t\u0259qdim edir, \u2013 deyir Bolsens. \u2013 Bu, sad\u0259c\u0259 adaptivlik v\u0259 yenid\u0259n konfiqurasiya olunma il\u0259 ba\u011fl\u0131 reklam deyil. B\u00fct\u00fcn vacib t\u0259tbiql\u0259rd\u0259 \u2013 ma\u015f\u0131n \u00f6yr\u0259nm\u0259, qraf analizi, y\u00fcks\u0259k s\u00fcr\u0259tli ticar\u0259t v\u0259 s. \u2013 onlar\u0131n t\u0259kc\u0259 m\u0259lumatlar\u0131n yay\u0131lmas\u0131 yolunu deyil, h\u0259m d\u0259 yadda\u015f arxitekturas\u0131n\u0131 \u2013 m\u0259lumatlar\u0131n \u00e7ip daxilind\u0259 nec\u0259 h\u0259r\u0259k\u0259t etdiyini konkret tap\u015f\u0131r\u0131\u011fa uy\u011funla\u015fd\u0131rmaq imkan\u0131 var. FPGA-larda dig\u0259r cihazlardan daha \u00e7ox yadda\u015f var. H\u0259m\u00e7inin, \u0259g\u0259r tap\u015f\u0131r\u0131q bir FPGA-ya s\u0131\u011fm\u0131rsa, bir ne\u00e7\u0259 \u00e7ipd\u0259 geni\u015fl\u0259ndirm\u0259k m\u00fcmk\u00fcnd\u00fcr, CPU v\u0259 ya GPU-lar\u0131n bir ne\u00e7\u0259 hiss\u0259sin\u0259 geni\u015fl\u0259ndirm\u0259k zaman\u0131 sizi g\u00f6zl\u0259y\u0259n \u00e7at\u0131\u015fmazl\u0131qlarla \u00fczl\u0259\u015fm\u0259d\u0259n.
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M\u0259nb\u0259: habr.com<\/a><\/p>","protected":false,"gt_translate_keys":[{"key":"rendered","format":"html"}]},"excerpt":{"rendered":"

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