{"id":103860,"date":"2022-04-23T21:36:37","date_gmt":"2022-04-23T19:36:38","guid":{"rendered":"https:\/\/prohoster.info\/blog\/novosti-interneta\/proekt-verigpu-razvivaet-otkrytyj-gpu-na-yazyke-verilog"},"modified":"2022-04-23T21:36:37","modified_gmt":"2022-04-23T19:36:38","slug":"proekt-verigpu-razvivaet-otkrytyj-gpu-na-yazyke-verilog","status":"publish","type":"post","link":"https:\/\/prohoster.info\/cs\/blog\/news\/proekt-verigpu-razvivaet-otkrytyj-gpu-na-yazyke-verilog","title":{"rendered":"Projekt VeriGPU vyv\u00edj\u00ed otev\u0159enou GPU v jazyce Verilog","gt_translate_keys":[{"key":"rendered","format":"text"}]},"content":{"rendered":"

Projekt VeriGPU je zam\u011b\u0159en na vytvo\u0159en\u00ed otev\u0159en\u00e9ho GPU, vyv\u00edjen\u00e9ho v jazyce pro popis a modelov\u00e1n\u00ed elektronick\u00fdch syst\u00e9m\u016f Verilog. P\u016fvodn\u011b je projekt vyv\u00edjen pomoc\u00ed simul\u00e1toru Verilog, ale po dokon\u010den\u00ed bude pou\u017eiteln\u00fd pro v\u00fdrobu skute\u010dn\u00fdch \u010dip\u016f. Zpr\u00e1vy o pokroku projektu jsou roz\u0161i\u0159ov\u00e1ny pod licenc\u00ed MIT. <\/p>\n

VeriGPU je prezentov\u00e1n jako specializovan\u00fd procesor (ASIC), optimalizovan\u00fd pro urychlen\u00ed v\u00fdpo\u010dt\u016f souvisej\u00edc\u00edch se syst\u00e9my strojov\u00e9ho u\u010den\u00ed. V pl\u00e1nech se zmi\u0148uje zaji\u0161t\u011bn\u00ed kompatibility s r\u00e1mcem hlubok\u00e9ho strojov\u00e9ho u\u010den\u00ed PyTorch a realizace mo\u017enosti v\u00fdvoje aplikac\u00ed pro VeriGPU pomoc\u00ed API HIP (Heterogeneous-Compute Interface). V budoucnu se nezavrhuje p\u0159id\u00e1n\u00ed podpory pro dal\u0161\u00ed API, jako jsou SYCL a NVIDIA CUDA. <\/p>\n

GPU je vyv\u00edjeno na z\u00e1klad\u011b instruk\u010dn\u00edho souboru RISC-V, ale kone\u010dn\u00e1 vnit\u0159n\u00ed architektura instruk\u010dn\u00edho souboru GPU je \u0161patn\u011b kompatibiln\u00ed s RISC-V ISA, proto\u017ee v p\u0159\u00edpadech, kdy n\u00e1vrh GPU neodpov\u00edd\u00e1 p\u0159edstav\u011b RISC-V, nen\u00ed c\u00edlem udr\u017een\u00ed kompatibility s RISC-V. V\u00fdvoj se zam\u011b\u0159uje na mo\u017enosti pot\u0159ebn\u00e9 pro syst\u00e9my strojov\u00e9ho u\u010den\u00ed, a proto pro zjednodu\u0161en\u00ed velikosti a slo\u017eitosti matice \u010dipu pou\u017e\u00edv\u00e1 pouze form\u00e1t v\u00fdpo\u010dt\u016f s plovouc\u00ed desetinnou \u010d\u00e1rkou BF16 a jsou k dispozici pouze po\u017eadovan\u00e9 operace s plovouc\u00ed desetinnou \u010d\u00e1rkou pro strojov\u00e9 u\u010den\u00ed, jako jsou exp, log, tanh a sqrt. <\/p>\n

Mezi dostupn\u00e9 komponenty pat\u0159\u00ed GPU \u0159adi\u010d, APU (zrychlen\u00e1 procesn\u00ed jednotka) pro celo\u010d\u00edseln\u00e9 operace (+, -, \/, *), blok pro operace s plovouc\u00ed desetinnou \u010d\u00e1rkou (+, *) a blok pro \u0159\u00edzen\u00ed v\u011btven\u00ed. Pro v\u00fdvoj aplikac\u00ed je k dispozici assembler a podpora kompilace k\u00f3du v C++ na z\u00e1klad\u011b LLVM. Mezi pl\u00e1novan\u00e9 funkce pat\u0159\u00ed paraleln\u00ed prov\u00e1d\u011bn\u00ed instrukc\u00ed, ukl\u00e1d\u00e1n\u00ed dat a instruk\u010dn\u00ed pam\u011bti do cache a operace SIMT (jedna instrukce, v\u00edce vl\u00e1ken).

\"Projekt<\/center>
\n
Zdroj: opennet.ru<\/a> <\/p>","protected":false,"gt_translate_keys":[{"key":"rendered","format":"html"}]},"excerpt":{"rendered":"

\u041f\u0440\u043e\u0435\u043a\u0442 VeriGPU \u043d\u0430\u0446\u0435\u043b\u0435\u043d \u043d\u0430 \u0441\u043e\u0437\u0434\u0430\u043d\u0438\u0435 \u043e\u0442\u043a\u0440\u044b\u0442\u043e\u0433\u043e GPU, \u0440\u0430\u0437\u0432\u0438\u0432\u0430\u0435\u043c\u043e\u0433\u043e \u043d\u0430 \u044f\u0437\u044b\u043a\u0435 \u043e\u043f\u0438\u0441\u0430\u043d\u0438\u044f \u0438 \u043c\u043e\u0434\u0435\u043b\u0438\u0440\u043e\u0432\u0430\u043d\u0438\u044f \u044d\u043b\u0435\u043a\u0442\u0440\u043e\u043d\u043d\u044b\u0445 \u0441\u0438\u0441\u0442\u0435\u043c Verilog. \u0418\u0437\u043d\u0430\u0447\u0430\u043b\u044c\u043d\u043e \u043f\u0440\u043e\u0435\u043a\u0442 \u0440\u0430\u0437\u0440\u0430\u0431\u0430\u0442\u044b\u0432\u0430\u0435\u0442\u0441\u044f \u0441 \u0438\u0441\u043f\u043e\u043b\u044c\u0437\u043e\u0432\u0430\u043d\u0438\u0435\u043c \u0441\u0438\u043c\u0443\u043b\u044f\u0442\u043e\u0440\u0430 Verilog, \u043d\u043e \u043f\u043e\u0441\u043b\u0435 \u0434\u043e\u0432\u0435\u0434\u0435\u043d\u0438\u044f \u0434\u043e \u0433\u043e\u0442\u043e\u0432\u043d\u043e\u0441\u0442\u0438 \u0441\u043c\u043e\u0436\u0435\u0442 \u0438\u0441\u043f\u043e\u043b\u044c\u0437\u043e\u0432\u0430\u0442\u044c\u0441\u044f \u0434\u043b\u044f \u043f\u0440\u043e\u0438\u0437\u0432\u043e\u0434\u0441\u0442\u0432\u0430 \u0440\u0435\u0430\u043b\u044c\u043d\u044b\u0445 \u0447\u0438\u043f\u043e\u0432. \u041d\u0430\u0440\u0430\u0431\u043e\u0442\u043a\u0438 \u043f\u0440\u043e\u0435\u043a\u0442\u0430 \u0440\u0430\u0441\u043f\u0440\u043e\u0441\u0442\u0440\u0430\u043d\u044f\u044e\u0442\u0441\u044f \u043f\u043e\u0434 \u043b\u0438\u0446\u0435\u043d\u0437\u0438\u0435\u0439 MIT. VeriGPU \u043f\u043e\u0437\u0438\u0446\u0438\u043e\u043d\u0438\u0440\u0443\u0435\u0442\u0441\u044f \u043a\u0430\u043a \u0441\u043f\u0435\u0446\u0438\u0430\u043b\u0438\u0437\u0438\u0440\u043e\u0432\u0430\u043d\u043d\u044b\u0439 \u043f\u0440\u043e\u0446\u0435\u0441\u0441\u043e\u0440 (ASIC), \u043e\u043f\u0442\u0438\u043c\u0438\u0437\u0438\u0440\u043e\u0432\u0430\u043d\u043d\u044b\u0439 \u0434\u043b\u044f \u0443\u0441\u043a\u043e\u0440\u0435\u043d\u0438\u044f \u0432\u044b\u0447\u0438\u0441\u043b\u0435\u043d\u0438\u0439, \u0441\u0432\u044f\u0437\u0430\u043d\u043d\u044b\u0445 \u0441 \u0441\u0438\u0441\u0442\u0435\u043c\u0430\u043c\u0438 \u043c\u0430\u0448\u0438\u043d\u043d\u043e\u0433\u043e \u043e\u0431\u0443\u0447\u0435\u043d\u0438\u044f. […]<\/p>\n","protected":false,"gt_translate_keys":[{"key":"rendered","format":"html"}]},"author":1,"featured_media":103861,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[702],"tags":[],"class_list":["post-103860","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-news"],"aioseo_notices":[],"aioseo_head":"\n\t\t\n\t\n\t\n\t\n\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\n","aioseo_head_json":{"title":"\ud83e\udd47Projekt VeriGPU vyv\u00edj\u00ed otev\u0159en\u00fd GPU v jazyce Verilog | ProHoster","description":"Projekt VeriGPU je zam\u011b\u0159en na vytvo\u0159en\u00ed otev\u0159en\u00e9ho GPU, vyv\u00edjen\u00e9ho v jazyce pro popis a modelov\u00e1n\u00ed elektronick\u00fdch syst\u00e9m\u016f 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