{"id":119157,"date":"2024-08-07T15:43:09","date_gmt":"2024-08-07T13:43:10","guid":{"rendered":"https:\/\/prohoster.info\/blog\/novosti-interneta\/dostupen-vortex-2-2-otkrytyj-gpgpu-na-baze-arhitektury-risc-v"},"modified":"2024-08-07T15:43:09","modified_gmt":"2024-08-07T13:43:10","slug":"dostupen-vortex-2-2-otkrytyj-gpgpu-na-baze-arhitektury-risc-v","status":"publish","type":"post","link":"https:\/\/prohoster.info\/cs\/blog\/news\/dostupen-vortex-2-2-otkrytyj-gpgpu-na-baze-arhitektury-risc-v","title":{"rendered":"Vortex 2.2 je dostupn\u00fd, otev\u0159en\u00fd GPGPU zalo\u017een\u00fd na architektu\u0159e RISC-V","gt_translate_keys":[{"key":"rendered","format":"text"}]},"content":{"rendered":"
Byla zve\u0159ejn\u011bna nov\u00e1 verze projektu Vortex 2.2, kter\u00fd vyv\u00edj\u00ed otev\u0159en\u00fd GPGPU na z\u00e1klad\u011b architektury RISC-V, zam\u011b\u0159en\u00fd na prov\u00e1d\u011bn\u00ed paraleln\u00edch v\u00fdpo\u010dt\u016f s vyu\u017eit\u00edm API OpenCL a modelu vykon\u00e1v\u00e1n\u00ed SIMT (Single Instruction, Multiple Threads). Projekt m\u016f\u017ee b\u00fdt rovn\u011b\u017e pou\u017eit pro v\u00fdzkum v oblasti 3D grafiky a p\u0159i v\u00fdvoji nov\u00fdch architektur GPU. Sch\u00e9mata, popisy hardwarov\u00fdch blok\u016f v jazyce Verilog, simul\u00e1tor, ovlada\u010de a souvisej\u00edc\u00ed projektov\u00e1 dokumentace jsou distribuov\u00e1ny pod licenc\u00ed Apache 2.0. <\/p>\n
Z\u00e1klad GPGPU tvo\u0159\u00ed standardn\u00ed ISA RISC-V, roz\u0161\u00ed\u0159en\u00fd o n\u011bkter\u00e9 dal\u0161\u00ed instrukce nezbytn\u00e9 pro podporu funkc\u00ed GPU a \u0159\u00edzen\u00ed vl\u00e1ken. P\u0159itom jsou zm\u011bny v architektu\u0159e p\u0159\u00edkazu RISC-V minimalizov\u00e1ny a co nejv\u00edce se vyu\u017e\u00edvaj\u00ed ji\u017e existuj\u00edc\u00ed vektorov\u00e9 instrukce. Mezi dal\u0161\u00ed instrukce pat\u0159\u00ed: «tex» pro zrychlen\u00ed zpracov\u00e1n\u00ed textur, vx_rast pro \u0159\u00edzen\u00ed rastrov\u00e1n\u00ed, vx_rop pro zpracov\u00e1n\u00ed fragment\u016f, hloubky a pr\u016fhlednosti, vx_imadd pro proveden\u00ed operace «n\u00e1sobit a s\u010d\u00edtat», vx_wspawn, vx_tmc a vx_bar pro aktivaci front instrukc\u00ed a vl\u00e1ken v nich (wavefront, sada vl\u00e1ken prov\u00e1d\u011bn\u00fdch paraleln\u011b SIMD Engine), vx_split a vx_join.
<\/center> <\/p>\n
Vyvinut\u00fd GPGPU podporuje 32- a 64bitov\u00e9 architektury RISC-V RV32IMF a RV64IMAFD a m\u016f\u017ee zahrnovat volitelnou sd\u00edlenou pam\u011b\u0165, ke\u0161 L1, L2 a L3, jako\u017e i p\u0159izp\u016fsobiteln\u00fd po\u010det jader, blok\u016f \u00faloh (warps) a vl\u00e1ken. Pro ka\u017ed\u00e9 j\u00e1dro je nav\u00edc k dispozici mo\u017enost aktivace p\u0159izp\u016fsobiteln\u00e9ho po\u010dtu ALU, FPU, LSU a SFU. Pro prototypov\u00e1n\u00ed lze pou\u017e\u00edt FPGA Altera Arria 10, Altera Stratix 10, Xilinx Alveo U50, U250, U280 a Xilinx Versal VCK5000. Pro simulaci \u010dinnosti \u010dipu mohou b\u00fdt vyu\u017eity Verilator (simul\u00e1tor Verilog), RTLSIM (simulace RTL) a SimX (softwarov\u00e1 simulace). <\/p>\n
Pro v\u00fdvoj aplikac\u00ed je k dispozici n\u00e1strojov\u00fd kit, kter\u00fd zahrnuje p\u0159izp\u016fsoben\u00e9 varianty PoCL (kompil\u00e1tor a runtime OpenCL) pro pr\u00e1ci s Vortex, LLVM\/Clang, GCC a Binutils. Projekt podporuje specifikaci OpenCL 1.2 a prost\u0159ednictv\u00edm p\u0159ekladu do OpenCL implementuje podporu pro meziprodukty shader\u016f SPIR-V. Pro grafiku na technologi\u00edch Vortex se vyv\u00edj\u00ed open-source GPU Skybox, kter\u00fd podporuje grafick\u00e9 API Vulkan. Prototyp Skybox, vytvo\u0159en\u00fd na b\u00e1zi FPGA Altera Stratix 10 a zahrnuj\u00edc\u00ed 32 jader (512 vl\u00e1ken), umo\u017enil p\u0159i frekvenci 230 MHz dos\u00e1hnout v\u00fdkonu pln\u011bn\u00ed 3,7 gigapixel\u016f za sekundu (29,4 gigatransakc\u00ed za sekundu). <\/p>\n
Mezi zm\u011bnami ve verzi Vortex 2.2: <\/p>\n
\n
P\u0159id\u00e1n API vx_spawn_taskgroups pro spu\u0161t\u011bn\u00ed jader, kter\u00e1 podporuj\u00ed segmentovan\u00e9 prov\u00e1d\u011bn\u00ed 3D \u00faloh.\n
P\u0159id\u00e1na podpora ZICOND, roz\u0161\u00ed\u0159en\u00ed architektury sady p\u0159\u00edkaz\u016f RISC-V, kter\u00e1 zaji\u0161\u0165uje podm\u00edn\u011bn\u00e9 prov\u00e1d\u011bn\u00ed operac\u00ed bez v\u011btven\u00ed.\n
Kompil\u00e1tor OpenCL byl p\u0159eveden na pl\u00e1nov\u00e1n\u00ed prov\u00e1d\u011bn\u00ed na \u00farovni jednotliv\u00fdch vl\u00e1ken (thread-level, ka\u017ed\u00e9 vl\u00e1kno prov\u00e1d\u00ed sv\u016fj \u00fakol nez\u00e1visle na ostatn\u00edch vl\u00e1knech), m\u00edsto skupin \u00faloh (warp-level), jak tomu bylo d\u0159\u00edve.\n
V OpenCL byla p\u0159id\u00e1na podpora JIT kompilace a 64bitov\u00fdch jader.\n
Byla implementov\u00e1na podpora dynamick\u00e9ho na\u010d\u00edt\u00e1n\u00ed Vortex runtime.\n
Byla navr\u017eena nov\u00e1 dokumentace pro nastaven\u00ed FPGA Xilinx.\n
Bylo zahrnuto testov\u00e1n\u00ed synt\u00e9zy logiky pomoc\u00ed n\u00e1strojov\u00e9ho kitu Yosys.\n
V hierarchick\u00fdch operac\u00edch flush a v re\u017eimu write-back byla zaji\u0161t\u011bna podpora cache.\n
Byla optimalizov\u00e1na rychlost scoreboard-verifikace a pr\u00e1ce s operandy na \u00farovni registr\u016f (RTL, Register Transfer Level).\n
Byla p\u0159id\u00e1na podpora simul\u00e1toru DRAM pam\u011bt\u00ed Ramulator 2.0.\n
Byl realizov\u00e1n p\u0159echod na pou\u017e\u00edv\u00e1n\u00ed nov\u00fdch verz\u00ed Verilator 5.0 (simul\u00e1tor SystemVerilog) a LLVM 18.0, a tak\u00e9 byl aktualizov\u00e1n n\u00e1strojov\u00fd kit na b\u00e1zi CentOS 7.9.\n
M\u00edsto syst\u00e9mu kontinu\u00e1ln\u00ed integrace Travis CI byl zaveden servis GitHub CI. <\/ul>\n
![\"Vortex](\"\/wp-content\/uploads\/2024\/08\/e9bf3436f9ea931993a04517f807fb72.png\")
<\/center> <\/p>\n