{"id":181998,"date":"2026-06-10T02:48:19","date_gmt":"2026-06-10T00:48:19","guid":{"rendered":"https:\/\/prohoster.info\/blog\/novosti-interneta\/opublikovan-vortex-3-0-otkrytyj-gpgpu-na-baze-arhitektury-risc-v"},"modified":"2026-06-10T02:48:19","modified_gmt":"2026-06-10T00:48:19","slug":"opublikovan-vortex-3-0-otkrytyj-gpgpu-na-baze-arhitektury-risc-v","status":"publish","type":"post","link":"https:\/\/prohoster.info\/cs\/blog\/news\/opublikovan-vortex-3-0-otkrytyj-gpgpu-na-baze-arhitektury-risc-v","title":{"rendered":"Bylo zve\u0159ejn\u011bno Vortex 3.0, otev\u0159en\u00fd GPGPU zalo\u017een\u00fd na architektu\u0159e RISC-V","gt_translate_keys":[{"key":"rendered","format":"text"}]},"content":{"rendered":"<p>Byl uvoln\u011bn projekt Vortex 3.0, kter\u00fd vyv\u00edj\u00ed otev\u0159en\u00fd GPGPU zalo\u017een\u00fd na architektu\u0159e instruk\u010dn\u00edho souboru RISC-V, ur\u010den\u00fd k prov\u00e1d\u011bn\u00ed paraleln\u00edch v\u00fdpo\u010dt\u016f pomoc\u00ed API OpenCL a modelu prov\u00e1d\u011bn\u00ed SIMT (Single Instruction, Multiple Threads). Projekt lze tak\u00e9 vyu\u017e\u00edt pro v\u00fdzkum v oblasti 3D grafiky a pro v\u00fdvoj nov\u00fdch architektur GPU. Sch\u00e9mata, popisy hardwarov\u00fdch blok\u016f v jazyce Verilog, simul\u00e1tor, ovlada\u010de a souvisej\u00edc\u00ed projektov\u00e1 dokumentace jsou k dispozici pod licenc\u00ed Apache 2.0. <\/p>\n<p>Z\u00e1kladem GPGPU je typick\u00fd ISA RISC-V, roz\u0161\u00ed\u0159en\u00fd o dal\u0161\u00ed instrukce na podporu funkc\u00ed GPU a \u0159\u00edzen\u00ed tok\u016f. Zm\u011bny v architektu\u0159e sady instrukc\u00ed RISC-V jsou minimalizov\u00e1ny a co nejv\u00edce vyu\u017e\u00edvaj\u00ed ji\u017e existuj\u00edc\u00ed vektorov\u00e9 instrukce. Mezi dal\u0161\u00ed instrukce pat\u0159\u00ed: \u201etex\u201c pro zrychlen\u00ed zpracov\u00e1n\u00ed textur; vx_rast pro \u0159\u00edzen\u00ed rastrov\u00e1n\u00ed, vx_rop pro zpracov\u00e1n\u00ed fragment\u016f, hloubky a pr\u016fhlednosti; vx_imadd pro proveden\u00ed operace \u201en\u00e1sobit a se\u010d\u00edst\u201c; vx_wspawn, vx_split, vx_join, vx_tmc a vx_bar pro aktivaci skupin tok\u016f (wavefront), paraleln\u011b prov\u00e1d\u011bn\u00fdch SIMD Engine. <\/p>\n<p><center><img decoding=\"async\" src=\"\/wp-content\/uploads\/2026\/06\/caa6274ce0dd622a2ebc01d60302d645.png\" style=\"display:block;margin: 0 auto;\" \/><\/center><\/p>\n<p>Vyv\u00edjen\u00fd GPGPU podporuje 32- a 64-bitov\u00e9 architektury instruk\u010dn\u00edho souboru RISC-V RV32IMF a RV64IMAFD, a m\u016f\u017ee zahrnovat volitelnou sd\u00edlenou pam\u011b\u0165, ke\u0161e \u00farovn\u00ed L1, L2 a L3, jako\u017e i nastaviteln\u00e9 mno\u017estv\u00ed jader, blok\u016f \u00faloh (warps) a vl\u00e1ken. Pro ka\u017ed\u00e9 j\u00e1dro je rovn\u011b\u017e mo\u017en\u00e9 aktivovat nastaviteln\u00e9 mno\u017estv\u00ed ALU, FPU, LSU a SFU. Pro vytv\u00e1\u0159en\u00ed prototyp\u016f lze pou\u017e\u00edt FPGA Xilinx a Altera, a pro simulaci \u010dipu lze aplikovat Verilator (Verilog simul\u00e1tor), RTLSIM (simulace RTL) a SimX (softwarov\u00e1 simulace).<\/p>\n<p>Pro v\u00fdvoj aplikac\u00ed je k dispozici n\u00e1strojov\u00fd set, kter\u00fd zahrnuje adaptovan\u00e9 verze PoCL (kompil\u00e1tor a runtime OpenCL) pro pr\u00e1ci s Vortex, LLVM\/Clang, GCC a Binutils. Projekt podporuje specifikaci OpenCL 1.2 a prost\u0159ednictv\u00edm p\u0159eklad\u016f do OpenCL implementuje podporu pro mezip\u0159edstaven\u00ed shader\u016f SPIR-V.  <\/p>\n<p>Mezi zm\u011bnami ve Vortex 3.0:<\/p>\n<ul>\n<li class=\"l\"> Byl p\u0159id\u00e1n hardwarov\u00fd grafick\u00fd z\u00e1sobn\u00edk, zahrnuj\u00edc\u00ed bloky pro rastrov\u00e1n\u00ed, p\u0159ekr\u00fdv\u00e1n\u00ed textur a slou\u010den\u00ed v\u00fdstupu (OM \u2014 Output Merger). Pro Mesa na b\u00e1zi realizovan\u00e9ho grafick\u00e9ho z\u00e1sobn\u00edku a softwarov\u00e9ho rastroviz\u00e1toru lavapipe byl p\u0159ipraven Vulkan ovlada\u010d vortexpipe.\n<li class=\"l\"> Byly roz\u0161\u00ed\u0159eny mo\u017enosti tenzorov\u00e9ho j\u00e1dra, kter\u00e9 je ur\u010deno pro zrychlen\u00ed prov\u00e1d\u011bn\u00ed model\u016f strojov\u00e9ho u\u010den\u00ed, a nyn\u00ed podporuje struktur\u00e1ln\u00ed sparsity pro kompresi v\u00e1hov\u00fdch matic.\n<li class=\"l\"> Byla implementov\u00e1na operace WGMMA (warpgroup-level matrix multiplication) pro n\u00e1soben\u00ed matic v asynchronn\u00edm re\u017eimu.\n<li class=\"l\"> Byl p\u0159id\u00e1n engine DXA (Data Transfer Acceleration) pro zrychlen\u00ed p\u0159enosu dat z glob\u00e1ln\u00ed do lok\u00e1ln\u00ed pam\u011bti.\n<li class=\"l\"> Byla realizov\u00e1na nov\u00e1 architektura zalo\u017een\u00e1 na procesoru p\u0159\u00edkaz\u016f (CP, Command Processor) a hardwarov\u00e9m pl\u00e1nova\u010di v\u00fdpo\u010detn\u00edch jader (KMU \u2014 Kernel Management Unit), kter\u00e1 umo\u017e\u0148uje p\u0159esunout na stran\u011b \u010dipu operace vyt\u011b\u017eov\u00e1n\u00ed v\u00fdpo\u010detn\u00edch tok\u016f.\n<li class=\"l\"> Byla navr\u017eena nov\u00e1 runtime knihovna funguj\u00edc\u00ed v neblokuj\u00edc\u00edm re\u017eimu, kter\u00e1 poskytuje abstrakce p\u0159eus\u0165uj\u00edc\u00ed v hardwarov\u011b asynchronn\u011b vykon\u00e1van\u00e9 p\u0159\u00edkazy. Podporov\u00e1ny jsou fronty, ud\u00e1losti, moduly a synchronizace na z\u00e1klad\u011b asynchronn\u00edch bari\u00e9r s semantikou arrive\/wait\/event.\n<li class=\"l\"> Byla p\u0159id\u00e1na podpora zkr\u00e1cen\u00fdch instrukc\u00ed RISC-V (RVC).\n<li class=\"l\"> Byla zrealizov\u00e1na hardwarov\u00e1 podpora atomick\u00fdch operac\u00ed (Hardware Atomics).\n<li class=\"l\"> Byl kompletn\u011b p\u0159epracov\u00e1n FPU a byly navr\u017eeny nov\u00e9 bloky n\u00e1sobi\u010d\u016f (Wallace-tree, Folded-radix) a s\u010d\u00edta\u010d\u016f (Kogge-Stone).\n<li class=\"l\"> Byl p\u0159id\u00e1n z\u00e1sobn\u00edk virtu\u00e1ln\u00ed pam\u011bti na z\u00e1klad\u011b bloku \u0159\u00edzen\u00ed pam\u011bti (MMU) s podporou 32-bitov\u00e9 architektury virtu\u00e1ln\u00ed adresace SV32.\n<li class=\"l\"> Podpora roz\u0161\u00ed\u0159en\u00ed RISC-V Zicond s realizac\u00ed podm\u00ednkov\u00fdch operac\u00ed.\n<li class=\"l\"> Integrovan\u00e9 \u0159\u00edzen\u00ed taktov\u00e1n\u00ed (clock gating).\n<li class=\"l\"> Byla implementov\u00e1na podpora jazyka HIP (Heterogeneous Interface for Portability) prost\u0159ednictv\u00edm frameworku chipStar, kter\u00fd p\u0159ekl\u00e1d\u00e1 HIP do SPIR-V.\n<li class=\"l\"> Byla zaji\u0161t\u011bna pln\u00e1 integrace se simul\u00e1torem GEM5 a byla p\u0159id\u00e1na podpora simul\u00e1toru SimX na architektu\u0159e TLM (Transaction-Level Modeling).\n<li class=\"l\"> Byla p\u0159id\u00e1na podpora n\u00e1stroj\u016f Synopsys a Yosys pro synt\u00e9zu logiky pro v\u00fdrobu \u010dip\u016f, stejn\u011b jako podpora pou\u017eit\u00ed knihoven standardn\u00edch prvk\u016f ASAP7 (7nm), SAED14 (14nm) a NanGate (15nm).\n<li class=\"l\"> Referen\u010dn\u00ed n\u00e1stroj byl aktualizov\u00e1n na LLVM 20 a POCL 7.0.\n<\/ul>\n<p>Zdroj: <a content=\"nofollow\" rel=\"nofollow\" href=\"https:\/\/www.opennet.ru\/opennews\/art.shtml?num=65652\">opennet.ru<\/a> <\/p>","protected":false,"gt_translate_keys":[{"key":"rendered","format":"html"}]},"excerpt":{"rendered":"<p>\u0414\u043e\u0441\u0442\u0443\u043f\u0435\u043d \u0432\u044b\u043f\u0443\u0441\u043a \u043f\u0440\u043e\u0435\u043a\u0442\u0430 Vortex 3.0, \u0440\u0430\u0437\u0432\u0438\u0432\u0430\u044e\u0449\u0435\u0433\u043e \u043e\u0442\u043a\u0440\u044b\u0442\u044b\u0439 GPGPU \u043d\u0430 \u0431\u0430\u0437\u0435 \u0430\u0440\u0445\u0438\u0442\u0435\u043a\u0442\u0443\u0440\u044b \u043d\u0430\u0431\u043e\u0440\u0430 \u043a\u043e\u043c\u0430\u043d\u0434 RISC-V, \u0440\u0430\u0441\u0441\u0447\u0438\u0442\u0430\u043d\u043d\u044b\u0439 \u043d\u0430 \u0432\u044b\u043f\u043e\u043b\u043d\u0435\u043d\u0438\u0435 \u043f\u0430\u0440\u0430\u043b\u043b\u0435\u043b\u044c\u043d\u044b\u0445 \u0432\u044b\u0447\u0438\u0441\u043b\u0435\u043d\u0438\u0439 \u0441 \u0438\u0441\u043f\u043e\u043b\u044c\u0437\u043e\u0432\u0430\u043d\u0438\u0435\u043c API OpenCL \u0438 \u043c\u043e\u0434\u0435\u043b\u0438 \u0432\u044b\u043f\u043e\u043b\u043d\u0435\u043d\u0438\u044f SIMT (Single Instruction, Multiple Threads). \u041f\u0440\u043e\u0435\u043a\u0442 \u0442\u0430\u043a\u0436\u0435 \u043c\u043e\u0436\u0435\u0442 \u0431\u044b\u0442\u044c \u0438\u0441\u043f\u043e\u043b\u044c\u0437\u043e\u0432\u0430\u043d \u043f\u0440\u0438 \u043f\u0440\u043e\u0432\u0435\u0434\u0435\u043d\u0438\u0438 \u0438\u0441\u0441\u043b\u0435\u0434\u043e\u0432\u0430\u043d\u0438\u0439 \u0432 \u043e\u0431\u043b\u0430\u0441\u0442\u0438 3D-\u0433\u0440\u0430\u0444\u0438\u043a\u0438 \u0438 \u043f\u0440\u0438 \u0440\u0430\u0437\u0440\u0430\u0431\u043e\u0442\u043a\u0435 \u043d\u043e\u0432\u044b\u0445 \u0430\u0440\u0445\u0438\u0442\u0435\u043a\u0442\u0443\u0440 GPU. \u0421\u0445\u0435\u043c\u044b, \u043e\u043f\u0438\u0441\u0430\u043d\u0438\u044f \u0430\u043f\u043f\u0430\u0440\u0430\u0442\u043d\u044b\u0445 \u0431\u043b\u043e\u043a\u043e\u0432 \u043d\u0430 \u044f\u0437\u044b\u043a\u0435 Verilog, [&hellip;]<\/p>\n","protected":false,"gt_translate_keys":[{"key":"rendered","format":"html"}]},"author":8,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[702],"tags":[],"class_list":["post-181998","post","type-post","status-publish","format-standard","hentry","category-news"],"aioseo_notices":[],"aioseo_head":"\n\t\t<!-- All in One SEO 5.0.3 - aioseo.com -->\n\t<meta name=\"description\" content=\"\u0414\u043e\u0441\u0442\u0443\u043f\u0435\u043d \u0432\u044b\u043f\u0443\u0441\u043a \u043f\u0440\u043e\u0435\u043a\u0442\u0430 Vortex 3.0, \u0440\u0430\u0437\u0432\u0438\u0432\u0430\u044e\u0449\u0435\u0433\u043e \u043e\u0442\u043a\u0440\u044b\u0442\u044b\u0439 GPGPU \u043d\u0430 \u0431\u0430\u0437\u0435 \u0430\u0440\u0445\u0438\u0442\u0435\u043a\u0442\u0443\u0440\u044b \u043d\u0430\u0431\u043e\u0440\u0430 \u043a\u043e\u043c\u0430\u043d\u0434 RISC-V, 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