{"id":56073,"date":"2020-02-04T00:00:00","date_gmt":"2020-02-03T21:00:00","guid":{"rendered":"https:\/\/prohoster.info\/blog\/blog_prohoster\/neizbezhnost-proniknoveniya-fpga-v-data-tsentry"},"modified":"2020-02-18T14:04:16","modified_gmt":"2020-02-18T11:04:16","slug":"neizbezhnost-proniknoveniya-fpga-v-data-tsentry","status":"publish","type":"post","link":"https:\/\/prohoster.info\/cs\/blog\/administrirovanie\/neizbezhnost-proniknoveniya-fpga-v-data-tsentry","title":{"rendered":"Nevyhnutelnost pronik\u00e1n\u00ed FPGA do datov\u00fdch center","gt_translate_keys":[{"key":"rendered","format":"text"}]},"content":{"rendered":"

\"Nevyhnutelnost
\nNen\u00ed t\u0159eba b\u00fdt v\u00fdvoj\u00e1\u0159em \u010dip\u016f, abyste programovali pro FPGA, stejn\u011b jako nen\u00ed nutn\u00e9 b\u00fdt program\u00e1torem v C++, abyste psali k\u00f3d v Jav\u011b. Nicm\u00e9n\u011b v obou p\u0159\u00edpadech to pravd\u011bpodobn\u011b nebude na \u0161kodu.<\/p>\n

C\u00edlem komercializace obou technologi\u00ed, Javy a FPGA, je vyvr\u00e1tit toto posledn\u00ed tvrzen\u00ed. Dobr\u00e9 zpr\u00e1vy pro FPGA - s vyu\u017eit\u00edm vhodn\u00fdch \u00farovn\u00ed abstrakce a n\u00e1stroj\u016f se v posledn\u00edch 35 letech, od doby, kdy byl vynalezen programovateln\u00e9 logick\u00e9 za\u0159\u00edzen\u00ed, st\u00e1v\u00e1 st\u00e1le snadn\u011bj\u0161\u00ed vytv\u00e1\u0159et algoritmy a datov\u00e9 toky pro FPGA m\u00edsto CPU, DSP, GPU nebo jak\u00e9koliv jin\u00e9 formy specializovan\u00fdch ASIC.<\/p>\n

Udivuj\u00edc\u00ed na\u010dasov\u00e1n\u00ed jejich vzniku spo\u010d\u00edv\u00e1 v tom, \u017ee pr\u00e1v\u011b kdy\u017e u\u017e CPU nemohly z\u016fstat jedin\u00fdm v\u00fdpo\u010detn\u00edm modulem, datov\u00e1 centra<\/a> aby splnily \u0159adu \u00fakol\u016f - z r\u016fzn\u00fdch d\u016fvod\u016f - FPGA dos\u00e1hly sv\u00e9 efektivity, nab\u00edzej\u00edc\u00ed vysok\u00fd v\u00fdkon, n\u00edzk\u00e9 latence, s\u00ed\u0165ov\u00e9 mo\u017enosti a pam\u011b\u0165 - rozmanit\u00e9 v\u00fdpo\u010detn\u00ed schopnosti modern\u00edch FPGA SoC, kter\u00e9 p\u0159edstavuj\u00ed prakticky plnohodnotn\u00e9 v\u00fdpo\u010detn\u00ed syst\u00e9my. Nicm\u00e9n\u011b FPGA se \u00fasp\u011b\u0161n\u011b kombinuj\u00ed i s jin\u00fdmi za\u0159\u00edzen\u00edmi v hybridn\u00edch syst\u00e9mech a podle na\u0161eho n\u00e1zoru teprve za\u010d\u00ednaj\u00ed nal\u00e9zat sv\u00e9 pr\u00e1voplatn\u00e9 m\u00edsto v hierarchii v\u00fdpo\u010dt\u016f.
\n<\/a><\/noindex>
\nProto jsme uspo\u0159\u00e1dali konferenci The Next FPGA Platform v San Jos\u00e9 22. ledna. Samoz\u0159ejm\u011b jedn\u00edm z hlavn\u00edch dodavatel\u016f FPGA na sv\u011bt\u011b a pr\u016fkopn\u00edkem v t\u00e9to oblasti je spole\u010dnost Xilinx. Ivo Bolens, senior viceprezident a technick\u00fd \u0159editel spole\u010dnosti Xilinx, vystoupil na konferenci s p\u0159edn\u00e1\u0161kou a pod\u011blil se s n\u00e1mi o sv\u00e9 dne\u0161n\u00ed my\u0161lenky na to, jak Xilinx pom\u00e1h\u00e1 vytv\u00e1\u0159et m\u011bniteln\u00e9 v\u00fdpo\u010detn\u00ed syst\u00e9my pro datov\u00e1 centra.<\/p>\n

Architekt\u016fm syst\u00e9m\u016f a program\u00e1tor\u016fm trvalo dost \u010dasu, ne\u017e p\u0159i\u0161li na my\u0161lenku heterogenn\u00edho datov\u00e9ho centra, kter\u00e9 by zahrnovalo r\u016fzn\u00e9 typy po\u010d\u00edta\u010dov\u00e9ho v\u00fdkonu, \u0159e\u0161\u00edc\u00ed \u00fakoly spojen\u00e9 s v\u00fdpo\u010dty, ukl\u00e1d\u00e1n\u00edm a organizac\u00ed s\u00edt\u00ed. To se zd\u00e1 b\u00fdt nutn\u00e9 vzhledem k tomu, \u017ee sledovat z\u00e1kon Moora pomoc\u00ed r\u016fzn\u00fdch CMOS se st\u00e1v\u00e1 st\u00e1le obt\u00ed\u017en\u011bj\u0161\u00edm. Na\u0161e terminologie se st\u00e1le zam\u011b\u0159uje na CPU a st\u00e1le hovo\u0159\u00edme o \u201ezrychlen\u00ed aplikac\u00ed\u201c, m\u00e1me na mysli zlep\u0161en\u00ed v\u00fdkonu program\u016f ve srovn\u00e1n\u00ed s t\u00edm, co je mo\u017en\u00e9 dos\u00e1hnout pouze na CPU. V budoucnu se datov\u00e1 centra prom\u011bn\u00ed v soubory v\u00fdpo\u010detn\u00edch v\u00fdkon\u016f, \u00falo\u017ei\u0161\u0165 dat a protokol\u016f, kter\u00e9 je v\u0161echno propojuj\u00ed, a vr\u00e1t\u00edme se k term\u00edn\u016fm jako \u201ev\u00fdpo\u010dty\u201c a \u201eaplikace\u201c. Hybridn\u00ed v\u00fdpo\u010dty se stanou normou, stejn\u011b jako dne\u0161n\u00ed \u201ecloudov\u00e9\u201c slu\u017eby, kter\u00e9 funguj\u00ed na z\u00e1klad\u011b b\u011b\u017en\u00fdch nebo virtu\u00e1ln\u00edch stroj\u016f<\/a>, a v ur\u010dit\u00e9m okam\u017eiku budeme pou\u017e\u00edvat pouze slovo \u201ev\u00fdpo\u010dty\u201c k popisu jejich fungov\u00e1n\u00ed. V ur\u010dit\u00e9m okam\u017eiku \u2013 a pravd\u011bpodobn\u011b tomu velmi pomohou FPGA \u2013 to znovu nazveme zpracov\u00e1n\u00edm dat.<\/p>\n

Aby bylo mo\u017en\u00e9 zav\u00e9st FPGA do datov\u00fdch center, je t\u0159eba zm\u011bnit zp\u016fsob my\u0161len\u00ed. \u201eP\u0159i uva\u017eov\u00e1n\u00ed o zp\u016fsobech, jak zrychlit dne\u0161n\u00ed aplikace, mus\u00edte proniknout do z\u00e1kladn\u00edch aspekt\u016f toho, jak jsou vykon\u00e1v\u00e1ny, jak\u00e9 zdroje se pou\u017e\u00edvaj\u00ed a na co se ztr\u00e1c\u00ed \u010das,\u201c vysv\u011btluje Bolsens. \u201eJe pot\u0159eba studovat celkov\u00fd probl\u00e9m, kter\u00fd se sna\u017e\u00edte vy\u0159e\u0161it. Mnoho aplikac\u00ed, kter\u00e9 dnes funguj\u00ed v datov\u00fdch centrech, je \u0161k\u00e1lov\u00e1no a zab\u00edr\u00e1 velk\u00e9 mno\u017estv\u00ed zdroj\u016f. Nap\u0159\u00edklad strojov\u00e9 u\u010den\u00ed, kter\u00e9 pou\u017e\u00edv\u00e1 obrovsk\u00e9 mno\u017estv\u00ed v\u00fdpo\u010detn\u00edch uzl\u016f. Ale kdy\u017e mluv\u00edme o zrychlen\u00ed, je t\u0159eba p\u0159em\u00fd\u0161let nejen o zrychlen\u00ed v\u00fdpo\u010dt\u016f, ale tak\u00e9 o zrychlen\u00ed infrastruktury.\"<\/p>\n

Nap\u0159\u00edklad u t\u011bch operac\u00ed spojen\u00fdch se strojov\u00fdm u\u010den\u00edm, kter\u00e9 Bolsens zkoumal v praxi, se p\u0159ibli\u017en\u011b 50 % \u010dasu ztr\u00e1c\u00ed na p\u0159enos dat sem a tam mezi rozpt\u00fdlen\u00fdmi v\u00fdpo\u010detn\u00edmi kapacitami, a pouze zb\u00fdvaj\u00edc\u00ed polovina \u010dasu se v\u011bnuje samotn\u00fdm v\u00fdpo\u010dt\u016fm.<\/p>\n

\u201ePr\u00e1v\u011b zde si mysl\u00edm, \u017ee m\u016f\u017ee FPGA pomoci, proto\u017ee m\u016f\u017eeme optimalizovat jak v\u00fdpo\u010detn\u00ed aspekty, tak aspekty p\u0159enosu dat pro aplikaci. A m\u016f\u017eeme to d\u011blat na \u00farovni obecn\u00e9 infrastruktury a na \u00farovni \u010dipu. To je jedna z velk\u00fdch v\u00fdhod FPGA, kter\u00e1 umo\u017e\u0148uje vytv\u00e1\u0159et komunika\u010dn\u00ed s\u00edt\u011b p\u0159izp\u016fsoben\u00e9 konkr\u00e9tn\u00edm pot\u0159eb\u00e1m aplikace. Kdy\u017e se d\u00edv\u00e1m na typick\u00e9 vzorce p\u0159enosu dat v \u00faloh\u00e1ch souvisej\u00edc\u00edch s um\u011blou inteligenc\u00ed, nevid\u00edm pot\u0159ebu slo\u017eit\u00e9 architektury na b\u00e1zi p\u0159ep\u00edna\u010d\u016f. M\u016f\u017eeme vybudovat s\u00ed\u0165 s velk\u00fdm datov\u00fdm tokem. To plat\u00ed i pro \u00falohy tr\u00e9nov\u00e1n\u00ed neuronov\u00fdch s\u00edt\u00ed \u2013 m\u016f\u017eeme vybudovat m\u0159\u00ed\u017ekovou s\u00ed\u0165 s velikostmi paket\u016f p\u0159izp\u016fsobuj\u00edc\u00edmi se konkr\u00e9tn\u00ed \u00faloze. S pou\u017eit\u00edm FPGA m\u016f\u017eeme velmi p\u0159esn\u011b \u0161k\u00e1lovat a p\u0159izp\u016fsobovat protokoly p\u0159enosu dat a topologii obvodu pro konkr\u00e9tn\u00ed aplikaci. A pokud jde o strojov\u00e9 u\u010den\u00ed, je tak\u00e9 jasn\u00e9, \u017ee nepot\u0159ebujeme \u010d\u00edsla s plovouc\u00ed desetinnou \u010d\u00e1rkou dvojit\u00e9 p\u0159esnosti, a to tak\u00e9 m\u016f\u017eeme p\u0159izp\u016fsobit.\u201c<\/p>\n

Rozd\u00edl mezi FPGA a CPU nebo specializovan\u00fdmi ASIC spo\u010d\u00edv\u00e1 v tom, \u017ee ty posledn\u011b jmenovan\u00e9 jsou naprogramov\u00e1ny p\u0159i v\u00fdrob\u011b a pot\u00e9 u\u017e nem\u016f\u017eete zm\u011bnit typy zpracov\u00e1van\u00fdch dat nebo zpracov\u00e1van\u00fdch prvk\u016f, ani povahu datov\u00e9ho toku proch\u00e1zej\u00edc\u00edho za\u0159\u00edzen\u00edm. FPGA v\u00e1m umo\u017e\u0148uj\u00ed zm\u011bnit n\u00e1zor, pokud se m\u011bn\u00ed provozn\u00ed podm\u00ednky.<\/p>\n

V minulosti byla tato v\u00fdhoda drah\u00e1, kdy\u017e programov\u00e1n\u00ed pro FPGA nebylo ur\u010deno pro slab\u00e9 povahy. Je nutn\u00e9 otev\u0159\u00edt kompil\u00e1tory pro FPGA, aby se l\u00e9pe integrovaly s n\u00e1stroji pou\u017e\u00edvan\u00fdmi program\u00e1tory pro vytv\u00e1\u0159en\u00ed aplikac\u00ed s paraleln\u00edmi v\u00fdpo\u010dty pro CPU v jazyc\u00edch C, C++ nebo Python, a sv\u011b\u0159it \u010d\u00e1st pr\u00e1ce knihovn\u00e1m, kter\u00e9 zrychluj\u00ed procedury na FPGA. To je pr\u00e1v\u011b to, co d\u011bl\u00e1 Vitis ML stack, kter\u00fd lemuje z\u00e1klady platforem pro ML, jako jsou Caffe a TensorFlow, a m\u00e1 knihovny pro spu\u0161t\u011bn\u00ed b\u011b\u017en\u00fdch AI model\u016f nebo p\u0159id\u00e1n\u00ed schopnost\u00ed FPGA k \u00faloh\u00e1m, jako jsou p\u0159ek\u00f3dov\u00e1n\u00ed videa, rozpozn\u00e1v\u00e1n\u00ed objekt\u016f ve videu, anal\u00fdza dat, \u0159\u00edzen\u00ed finan\u010dn\u00edch rizik a jak\u00e9koli extern\u00ed knihovny.<\/p>\n

Tato koncepce se p\u0159\u00edli\u0161 neli\u0161\u00ed od projektu CUDA od Nvidie, kter\u00fd byl spu\u0161t\u011bn p\u0159ed deseti lety a p\u0159en\u00e1\u0161el paraleln\u00ed v\u00fdpo\u010dty na GPU akceler\u00e1tory, nebo od n\u00e1stroje ROCm od AMD, \u010di od slib\u016f projektu Intel, OneAPI, kter\u00fd m\u00e1 fungovat na r\u016fzn\u00fdch CPU, GPU a FPGA.<\/p>\n

Ot\u00e1zka zn\u00ed, jak budou v\u0161echny tyto n\u00e1stroje spojeny dohromady, aby si kdokoli mohl naprogramovat sadu v\u00fdpo\u010detn\u00edch v\u00fdkon\u016f podle sv\u00fdch pot\u0159eb. To je d\u016fle\u017eit\u00e9, proto\u017ee FPGA se staly slo\u017eit\u011bj\u0161\u00edmi, mnohem slo\u017eit\u011bj\u0161\u00edmi ne\u017e jak\u00e9koli dostupn\u00e9 CPU. Jsou vyr\u00e1b\u011bny nejmodern\u011bj\u0161\u00edmi technologick\u00fdmi procesy a pomoc\u00ed nejmodern\u011bj\u0161\u00edch technologi\u00ed balen\u00ed \u010dip\u016f. A najdou si svou niku, proto\u017ee si u\u017e nem\u016f\u017eeme dovolit pl\u00fdtvat \u010dasem, pen\u011bzi, energi\u00ed a inteligenc\u00ed \u2013 to v\u0161echno jsou p\u0159\u00edli\u0161 drah\u00e9 zdroje.<\/p>\n

\u201eFPGA nab\u00edzej\u00ed technologick\u00e9 v\u00fdhody,\u201c \u0159\u00edk\u00e1 Bolsens. \u201eA to nen\u00ed jen b\u011b\u017en\u00e1 reklama o p\u0159izp\u016fsobivosti a p\u0159eprogramovatelnosti. Ve v\u0161ech d\u016fle\u017eit\u00fdch aplikac\u00edch \u2013 strojov\u00e9 u\u010den\u00ed, anal\u00fdza graf\u016f, vysokorychlostn\u00ed obchodov\u00e1n\u00ed atd. \u2013 maj\u00ed mo\u017enost p\u0159izp\u016fsobit nejen cestu \u0161\u00ed\u0159en\u00ed dat konkr\u00e9tn\u00ed \u00faloze, ale i architekturu pam\u011bti \u2013 jak se data pohybuj\u00ed v r\u00e1mci \u010dipu. A nav\u00edc maj\u00ed FPGA mnohem v\u00edce pam\u011bti ne\u017e jin\u00e1 za\u0159\u00edzen\u00ed. Je tak\u00e9 t\u0159eba vz\u00edt v \u00favahu, \u017ee pokud \u00faloha nevyhovuje jednomu FPGA, lze ji \u0161k\u00e1lovat na n\u011bkolik \u010dip\u016f, ani\u017e byste narazili na nev\u00fdhody, kter\u00e9 v\u00e1s \u010dekaj\u00ed p\u0159i \u0161k\u00e1lov\u00e1n\u00ed \u00faloh na n\u011bkolika CPU nebo GPU.\u201c
\n
Zdroj: habr.com<\/a><\/p>","protected":false,"gt_translate_keys":[{"key":"rendered","format":"html"}]},"excerpt":{"rendered":"

\u041d\u0435 \u043d\u0443\u0436\u043d\u043e \u0431\u044b\u0442\u044c \u0440\u0430\u0437\u0440\u0430\u0431\u043e\u0442\u0447\u0438\u043a\u043e\u043c \u0447\u0438\u043f\u043e\u0432, \u0447\u0442\u043e\u0431\u044b \u043f\u0440\u043e\u0433\u0440\u0430\u043c\u043c\u0438\u0440\u043e\u0432\u0430\u0442\u044c \u0434\u043b\u044f FPGA, \u043a\u0430\u043a \u043d\u0435 \u043d\u0443\u0436\u043d\u043e \u0431\u044b\u0442\u044c \u043f\u0440\u043e\u0433\u0440\u0430\u043c\u043c\u0438\u0441\u0442\u043e\u043c \u043d\u0430 \u0421++, \u0447\u0442\u043e\u0431\u044b \u043f\u0438\u0441\u0430\u0442\u044c \u043a\u043e\u0434 \u043d\u0430 Java. \u041e\u0434\u043d\u0430\u043a\u043e \u0432 \u043e\u0431\u043e\u0438\u0445 \u0441\u043b\u0443\u0447\u0430\u044f\u0445, \u0432\u0435\u0440\u043e\u044f\u0442\u043d\u043e, \u044d\u0442\u043e \u0431\u0443\u0434\u0435\u0442 \u043d\u0435 \u043b\u0438\u0448\u043d\u0438\u043c. \u0426\u0435\u043b\u044c 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