{"id":77492,"date":"2020-04-10T19:42:45","date_gmt":"2020-04-10T17:42:45","guid":{"rendered":"https:\/\/prohoster.info\/blog\/novosti-interneta\/poberegis-arm-novye-64-razryadnye-yadra-synopsys-arc-uvelichat-proizvoditelnost-vtroe"},"modified":"2020-04-10T19:42:45","modified_gmt":"2020-04-10T17:42:45","slug":"poberegis-arm-novye-64-razryadnye-yadra-synopsys-arc-uvelichat-proizvoditelnost-vtroe","status":"publish","type":"post","link":"https:\/\/prohoster.info\/cs\/blog\/news\/poberegis-arm-novye-64-razryadnye-yadra-synopsys-arc-uvelichat-proizvoditelnost-vtroe","title":{"rendered":"Pozor, ARM? Nov\u00e1 64-bitov\u00e1 j\u00e1dra Synopsys ARC ztrojn\u00e1sob\u00ed v\u00fdkon","gt_translate_keys":[{"key":"rendered","format":"text"}]},"content":{"rendered":"

M\u00e1lo kdo v\u00ed, \u017ee procesorov\u00e1 architektura ARC pat\u0159\u00ed mezi nejroz\u0161\u00ed\u0159en\u011bj\u0161\u00ed architektury vedle ARM, MIPS a x86. Vyvinut\u00e1 v 80. letech, architektura ARC se pou\u017e\u00edv\u00e1 v r\u016fzn\u00fdch mikrokontrolerech pro \u0161irok\u00e9 spektrum vysoce technologick\u00fdch produkt\u016f, p\u0159i\u010dem\u017e ka\u017ed\u00fd rok se na z\u00e1klad\u011b ARC vyr\u00e1b\u00ed p\u0159ibli\u017en\u011b 1,5 miliardy<\/a><\/noindex> za\u0159\u00edzen\u00ed.<\/p>\n

Ned\u00e1vno spole\u010dnost Synopsys ozn\u00e1mila novou generaci 32- a 64-bitov\u00fdch procesorov\u00fdch jader ARC, kter\u00e1 slibuj\u00ed trojn\u00e1sobn\u00e9 zv\u00fd\u0161en\u00ed v\u00fdkonu oproti p\u0159edch\u016fdc\u016fm a umo\u017en\u00ed stav\u011bt syst\u00e9my na \u010dipu s 12 j\u00e1dry. T\u00edmto zp\u016fsobem nov\u00e1 j\u00e1dra umo\u017en\u00ed Synopsys konkurovat ARM v n\u011bkolika nov\u00fdch oblastech.<\/p>\n

«Integrovan\u00e9 aplikace jako \u0159adi\u010de pro SSD nebo s\u00ed\u0165ov\u00e1 za\u0159\u00edzen\u00ed se st\u00e1vaj\u00ed st\u00e1le slo\u017eit\u011bj\u0161\u00edmi, co\u017e vy\u017eaduje zna\u010dn\u00e9 zv\u00fd\u0161en\u00ed v\u00fdkonu p\u0159i omezen\u00e9 spot\u0159eb\u011b energie a velikosti», — \u0159ekl John Koeter, senior viceprezident pro marketing a strategii du\u0161evn\u00edho vlastnictv\u00ed ve spole\u010dnosti Synopsys. «S uveden\u00edm nov\u00e9 architektury ARCv3 a jader ARC HS5x a HS6x budou m\u00edt v\u00fdvoj\u00e1\u0159i mo\u017enost splnit rostouc\u00ed po\u017eadavky na v\u00fdkon sv\u00fdch SoC dnes a v budoucnosti».<\/p>\n

\"Pozor,
\n<\/center><\/p>\n

Nov\u00e9 rodiny procesor\u016f Synopsys DesignWare ARC zahrnuj\u00ed 32-bitov\u00e1 j\u00e1dra HS56\/HS57D\/HS58<\/a><\/noindex> a 64-bitov\u00e1 j\u00e1dra HS66\/HS68<\/a><\/noindex>. Nov\u011b ozn\u00e1men\u00e9 procesory jsou ur\u010deny pro \u0161irokou \u0161k\u00e1lu aplikac\u00ed, jako jsou \u0159adi\u010de pro SSD, s\u00ed\u0165ov\u00e9 \u0159adi\u010de, autopiloty pro vozidla, infotainmentov\u00e9 syst\u00e9my pro automobily a mnoho dal\u0161\u00edch. Vzhledem k rostouc\u00edm po\u017eadavk\u016fm na objemy pam\u011bti umo\u017en\u00ed 64-bitov\u00e9 ARC HD6x vytv\u00e1\u0159et syst\u00e9my s 4,5 PB DRAM, zat\u00edmco za\u0159\u00edzen\u00ed zalo\u017een\u00e1 na ARC HD5x se budou muset omezit na men\u0161\u00ed objemy. Nicm\u00e9n\u011b skute\u010dn\u00e9 objemy podporovan\u00e9 pam\u011bti sp\u00ed\u0161e ur\u010d\u00ed pou\u017eit\u00e9 opera\u010dn\u00ed syst\u00e9my, zat\u00edmco viditeln\u00e9 v\u00fdhody 64-bitov\u00fdch CPU budou spo\u010d\u00edvat ve \u0161ir\u0161\u00edch front\u00e1ch a v\u011bt\u0161\u00edch souborech registr\u016f.<\/p>\n

Pokud jde o architektury DesignWare ARC HS5x a DesignWare ARC HS6x, podporuj\u00ed sadu p\u0159\u00edkaz\u016f ARCv3, kter\u00e1 m\u016f\u017ee b\u00fdt roz\u0161\u00ed\u0159ena o instrukce APEX (ARC Processor EXtensions), pokud by n\u011bjak\u00e9mu z klient\u016f bylo pot\u0159eba n\u011bco specifick\u00e9ho. Krom\u011b toho je ARC HS57D vybaven digit\u00e1ln\u00edm sign\u00e1ln\u00edm procesorem ARCv3DSP s podporou 150 instrukc\u00ed. Nov\u00e1 j\u00e1dra maj\u00ed hloubku pipeline 10 \u00farovn\u00ed, mohou vykon\u00e1vat dv\u011b instrukce na takt a jsou vybavena 128-bitov\u00fdm modulus pro operace s plovouc\u00ed desetinou. P\u0159i\u010dem\u017e nejpokro\u010dilej\u0161\u00ed verze jader podporuj\u00ed druhou \u00farove\u0148 cache (L2) o velikosti a\u017e 16 MB.<\/p>\n

\"Pozor,<\/p>\n

Pokud jde o v\u00fdkon, Synopsys uv\u00e1d\u00ed 3 DMIPS na MHz v celo\u010d\u00edseln\u00fdch v\u00fdpo\u010dtech a tak\u00e9 5,1 CoreMark na MHz, co\u017e je velmi dobr\u00e9 pro miniaturizovan\u00e1 j\u00e1dra s minim\u00e1ln\u00ed spot\u0159ebou energie. Tak\u017ee 3 DMIPS na MHz  — to je v\u00edce ne\u017e u pom\u011brn\u011b v\u00fdkonn\u00fdch procesor\u016f Cortex-A55<\/a><\/noindex>, zat\u00edmco 5,1 CoreMark na MHz — je v\u00edce ne\u017e u jak\u00e9hokoliv procesoru ARM pro mikrokontrol\u00e9ry.<\/a><\/noindex><\/p>\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n

Procesorov\u00e1 j\u00e1dra Synopsys DesignWare ARC HS5x a HS6x
<\/strong><\/p>\n<\/td>\n<\/tr>\n

<\/td>\nHS5x<\/td>\nHS6x<\/td>\n<\/tr>\n
<\/td>\nHS56<\/td>\nHS57D<\/td>\nHS58<\/td>\nHS66<\/td>\nHS68<\/td>\n<\/tr>\n
Sada p\u0159\u00edkaz\u016f<\/td>\nARCv3<\/td>\n<\/tr>\n
Instrukce APEX<\/td>\nPodporov\u00e1no<\/td>\n<\/tr>\n
\u0160\u00ed\u0159ka slova<\/td>\n32 bit\u016f<\/td>\n64 bit\u016f<\/td>\n<\/tr>\n
Instrukc\u00ed za takt<\/td>\n2<\/td>\n<\/tr>\n
D\u00e9lka pipeline<\/td>\n10 \u00farovn\u00ed<\/td>\n<\/tr>\n
DSP<\/td>\n—<\/td>\nARCv3DSP
150 instrukc\u00ed<\/td>\n		—<\/td>\n—<\/td>\n—<\/td>\n<\/tr>\n
P\u0159esnost FPU<\/td>\nFP16, FP32, FP64<\/td>\n<\/tr>\n
Procesorov\u00fd cluster<\/td>\n12 jader<\/td>\n<\/tr>\n
Zrychlova\u010d\u016f na cluster<\/td>\n16 zrychlova\u010d\u016f<\/td>\n<\/tr>\n
L1<\/td>\nCache instrukc\u00ed + Cache dat<\/td>\n<\/tr>\n
L2<\/td>\n—<\/td>\n—<\/td>\n16 MB<\/td>\n—<\/td>\n16 MB<\/td>\n<\/tr>\n
Maxim\u00e1ln\u00ed velikost pam\u011bti<\/td>\n64 GB (z\u00e1vis\u00ed na OS)<\/td>\n4,5 Petabyt\u016f<\/td>\n<\/tr>\n
Frekvence (na t\/p 16FFC)<\/td>\n1,8 GHz<\/td>\n<\/tr>\n
DMIPS<\/td>\n5400 DMIPS na j\u00e1dro \/ 3 DMIPS na MHz<\/td>\n<\/tr>\n
CoreMark<\/td>\n9180 CoreMark na j\u00e1dro \/ 5,1 CoreMark na MHz<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

Jednou z kl\u00ed\u010dov\u00fdch vlastnost\u00ed nov\u00e9 rodiny DesignWare ARC HS5x a DesignWare ARC HS6x je mo\u017enost vytv\u00e1\u0159et syst\u00e9my na \u010dipu (SoC) se 12 procesorov\u00fdmi j\u00e1dry obecn\u00e9ho ur\u010den\u00ed a 16 specializovan\u00fdmi zrychlova\u010di. Ka\u017ed\u00e9 j\u00e1dro\/zrychlova\u010d v takov\u00e9m procesoru pracuje na vlastn\u00ed taktovac\u00ed frekvenci a vyu\u017e\u00edv\u00e1 vlastn\u00ed nap\u00e1jec\u00ed subsyst\u00e9m pro maximalizaci energetick\u00e9 \u00fa\u010dinnosti. Spolu s nov\u00fdmi j\u00e1dry nab\u00edz\u00ed Synopsys tak\u00e9 intraprocesorov\u00e9 cache koherentn\u00ed spojen\u00ed s p\u0159enosovou rychlost\u00ed 800 GB\/s. <\/p>\n

Takov\u00e9to SoC zalo\u017een\u00e9 na architektu\u0159e ARC nejsou dnes p\u0159\u00edli\u0161 roz\u0161\u00ed\u0159en\u00e9, ale vzhledem k perspektivn\u00edm procesor\u016fm pro syst\u00e9my autonomn\u00edho \u0159\u00edzen\u00ed, ukl\u00e1d\u00e1n\u00ed dat, spr\u00e1vu toku dat, v\u00edce j\u00e1drech a r\u016fzn\u00fdm akceler\u00e1tor\u016fm se uk\u00e1\u017eou jako velmi u\u017eite\u010dn\u00e9. To posledn\u00ed umo\u017en\u00ed spole\u010dnosti Synopsys konkurovat j\u00e1dr\u016fm ARM o m\u00edsto v SoC pro uveden\u00e9 aplikace, k \u010demu\u017e dosud nedo\u0161lo. Tak v\u00fdrobci pevn\u00fdch disk\u016f Starblaze u\u017e projevili z\u00e1jem o j\u00e1dra DesignWare ARC HS5x a DesignWare ARC HS6x. <\/p>\n

«V\u00fdvoj\u00e1\u0159i vysoce v\u00fdkonn\u00fdch integrovan\u00fdch \u0159e\u0161en\u00ed se neust\u00e1le setk\u00e1vaj\u00ed s nov\u00fdmi v\u00fdzvami v oblasti dosa\u017een\u00ed vysok\u00e9ho v\u00fdkonu p\u0159i vyu\u017eit\u00ed velk\u00fdch objem\u016f pam\u011bti a omezen\u00edch v oblasti spot\u0159eby energie a velikosti», — \u0159ekl Bruce Cheng, hlavn\u00ed v\u011bdeck\u00fd pracovn\u00edk spole\u010dnosti Starblaze. «Mo\u017enosti nov\u00fdch 32-bitov\u00fdch procesor\u016f ARC HS5x a 64-bitov\u00fdch procesor\u016f HS6x spole\u010dnosti Synopsys v oblasti multij\u00e1drovosti n\u00e1m umo\u017en\u00ed dos\u00e1hnout nov\u00e9 \u00farovn\u011b efektivity spot\u0159eby energie, kterou nenab\u00edz\u00ed \u017e\u00e1dn\u00e9 jin\u00e9 procesory dostupn\u00e9 na trhu dnes».<\/p>\n

\"Pozor,<\/p>\n

Spole\u010dnost Synopsys za\u010dne nab\u00edzet j\u00e1dra ARC HS56, HS57D, HS58, HS66, HS68, a tak\u00e9 jejich v\u00edcej\u00e1drov\u00e9 verze HS56MP, HS57DMP, HS58MP, HS66MP, HS68MP, po\u010d\u00ednaje t\u0159et\u00edm \u010dtvrtlet\u00edm 2020. Krom\u011b toho nab\u00eddne bal\u00edk ARC MetaWare Development Toolkit pro vytv\u00e1\u0159en\u00ed \u010dip\u016f na z\u00e1klad\u011b uveden\u00fdch jader, a tak\u00e9 simul\u00e1tor a verifier pro testov\u00e1n\u00ed funk\u010dnosti SoC p\u0159ed jejich realizac\u00ed v k\u0159em\u00edku. Co se t\u00fd\u010de podpory opera\u010dn\u00edch syst\u00e9m\u016f, budou nov\u00e1 j\u00e1dra kompatibiln\u00ed s \u0159adou distribuc\u00ed Linux, Zephyr, a tak\u00e9 r\u016fzn\u00fdmi vlastn\u00edmi OS.<\/p>\n

<\/p>\n

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Zdroj: 3dnews.ru<\/a> <\/p>","protected":false,"gt_translate_keys":[{"key":"rendered","format":"html"}]},"excerpt":{"rendered":"

\u041d\u0435\u043c\u043d\u043e\u0433\u0438\u0435 \u0437\u043d\u0430\u044e\u0442, \u0447\u0442\u043e \u043f\u0440\u043e\u0446\u0435\u0441\u0441\u043e\u0440\u043d\u0430\u044f \u0430\u0440\u0445\u0438\u0442\u0435\u043a\u0442\u0443\u0440\u0430 ARC \u044f\u0432\u043b\u044f\u0435\u0442\u0441\u044f \u043e\u0434\u043d\u043e\u0439 \u0438\u0437 \u0441\u0430\u043c\u044b\u0445 \u0440\u0430\u0441\u043f\u0440\u043e\u0441\u0442\u0440\u0430\u043d\u0435\u043d\u043d\u044b\u0445 \u0430\u0440\u0445\u0438\u0442\u0435\u043a\u0442\u0443\u0440 \u043d\u0430\u0440\u044f\u0434\u0443 \u0441 ARM, MIPS \u0438 x86. \u0420\u0430\u0437\u0440\u0430\u0431\u043e\u0442\u0430\u043d\u043d\u0430\u044f \u0432 1980-\u0445 \u0433\u043e\u0434\u0430\u0445, \u0430\u0440\u0445\u0438\u0442\u0435\u043a\u0442\u0443\u0440\u0430 ARC \u043f\u0440\u0438\u043c\u0435\u043d\u044f\u0435\u0442\u0441\u044f \u0432 \u0440\u0430\u0437\u043b\u0438\u0447\u043d\u044b\u0445 \u043c\u0438\u043a\u0440\u043e\u043a\u043e\u043d\u0442\u0440\u043e\u043b\u043b\u0435\u0440\u0430\u0445 \u0434\u043b\u044f \u0448\u0438\u0440\u043e\u0447\u0430\u0439\u0448\u0435\u0433\u043e \u0441\u043f\u0435\u043a\u0442\u0440\u0430 \u0432\u044b\u0441\u043e\u043a\u043e\u0442\u0435\u0445\u043d\u043e\u043b\u043e\u0433\u0438\u0447\u043d\u043e\u0439 \u043f\u0440\u043e\u0434\u0443\u043a\u0446\u0438\u0438, \u0430 \u043a\u0430\u0436\u0434\u044b\u0439 \u0433\u043e\u0434 \u043d\u0430 \u043e\u0441\u043d\u043e\u0432\u0435 ARC \u043f\u0440\u043e\u0438\u0437\u0432\u043e\u0434\u0438\u0442\u0441\u044f \u043e\u043a\u043e\u043b\u043e 1,5 \u043c\u0438\u043b\u043b\u0438\u0430\u0440\u0434\u0430 \u0443\u0441\u0442\u0440\u043e\u0439\u0441\u0442\u0432. \u041d\u0430 \u0434\u043d\u044f\u0445 \u043a\u043e\u0440\u043f\u043e\u0440\u0430\u0446\u0438\u044f Synopsys \u0430\u043d\u043e\u043d\u0441\u0438\u0440\u043e\u0432\u0430\u043b\u0430 \u043d\u043e\u0432\u043e\u0435 \u043f\u043e\u043a\u043e\u043b\u0435\u043d\u0438\u0435 32- \u0438 64-\u0440\u0430\u0437\u0440\u044f\u0434\u043d\u044b\u0445 \u043f\u0440\u043e\u0446\u0435\u0441\u0441\u043e\u0440\u043d\u044b\u0445 […]<\/p>\n","protected":false,"gt_translate_keys":[{"key":"rendered","format":"html"}]},"author":1,"featured_media":77493,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[702],"tags":[],"class_list":["post-77492","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-news"],"aioseo_notices":[],"aioseo_head":"\n\t\t\n\t\n\t\n\t\n\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\n","aioseo_head_json":{"title":"\ud83e\udd47Pozor, ARM? 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