{"id":87136,"date":"2020-07-04T01:42:40","date_gmt":"2020-07-03T23:42:40","guid":{"rendered":"https:\/\/prohoster.info\/blog\/administrirovanie\/simulyatory-kompyuternyh-sistem-vsem-znakomyj-polnoplatformennyj-simulyator-i-nikomu-neizvestnye-potaktovyj-i-trassy"},"modified":"2020-07-04T01:42:40","modified_gmt":"2020-07-03T23:42:40","slug":"simulyatory-kompyuternyh-sistem-vsem-znakomyj-polnoplatformennyj-simulyator-i-nikomu-neizvestnye-potaktovyj-i-trassy","status":"publish","type":"post","link":"https:\/\/prohoster.info\/cs\/blog\/administrirovanie\/simulyatory-kompyuternyh-sistem-vsem-znakomyj-polnoplatformennyj-simulyator-i-nikomu-neizvestnye-potaktovyj-i-trassy","title":{"rendered":"Simul\u00e1tory po\u010d\u00edta\u010dov\u00fdch syst\u00e9m\u016f: zn\u00e1m\u00fd multiplatformn\u00ed simul\u00e1tor a nikdo nezn\u00e1 taktick\u00e9 a z\u00e1vodn\u00ed simul\u00e1tory","gt_translate_keys":[{"key":"rendered","format":"text"}]},"content":{"rendered":"

Ve druh\u00e9 \u010d\u00e1sti \u010dl\u00e1nku o simul\u00e1torech po\u010d\u00edta\u010dov\u00fdch syst\u00e9m\u016f budu pokra\u010dovat v jednodu\u0161e srozumiteln\u00e9m vypr\u00e1v\u011bn\u00ed o po\u010d\u00edta\u010dov\u00fdch simul\u00e1torech, konkr\u00e9tn\u011b o plnohodnotn\u00e9 simulaci, se kterou se b\u011b\u017en\u00fd u\u017eivatel setk\u00e1v\u00e1 nej\u010dast\u011bji, a tak\u00e9 o taktick\u00e9m modelu a trat\u00edch, kter\u00e9 jsou popul\u00e1rn\u011bj\u0161\u00ed mezi v\u00fdvoj\u00e1\u0159i. <\/p>\n

\"Simul\u00e1tory
\n<\/a><\/noindex>
\nV prvn\u00ed \u010d\u00e1sti<\/a><\/noindex> Hovo\u0159il jsem o tom, co simul\u00e1tory vlastn\u011b jsou, a tak\u00e9 o \u00farovn\u00edch modelov\u00e1n\u00ed. Nyn\u00ed, na z\u00e1klad\u011b t\u011bchto znalost\u00ed, navrhuji pono\u0159it se o n\u011bco hloub\u011bji a probrat plnohodnotnou simulaci, jak sestavit trat\u011b, co s nimi pak d\u011blat, a tak\u00e9 o taktick\u00e9 mikroarchitektonick\u00e9 emulaci. <\/p>\n

Plnohodnotn\u00fd simul\u00e1tor (full platform simulator), nebo \"Jeden v poli \u2014 nen\u00ed voj\u00e1k\" <\/h3>\n

\nPokud je t\u0159eba prozkoumat funkci jednoho konkr\u00e9tn\u00edho za\u0159\u00edzen\u00ed, nap\u0159\u00edklad s\u00ed\u0165ov\u00e9 karty, nebo napsat pro toto za\u0159\u00edzen\u00ed firmware nebo ovlada\u010d, mohou b\u00fdt tato za\u0159\u00edzen\u00ed modelov\u00e1na samostatn\u011b. Nicm\u00e9n\u011b pou\u017e\u00edvat je mimo ostatn\u00ed infrastrukturu nen\u00ed p\u0159\u00edli\u0161 pohodln\u00e9. Pro spu\u0161t\u011bn\u00ed p\u0159\u00edslu\u0161n\u00e9ho ovlada\u010de je pot\u0159eba centr\u00e1ln\u00ed procesor, pam\u011b\u0165, p\u0159\u00edstup k sb\u011brnici pro p\u0159enos dat a dal\u0161\u00ed. Krom\u011b toho je pro fungov\u00e1n\u00ed ovlada\u010de nezbytn\u00fd opera\u010dn\u00ed syst\u00e9m (OS) a s\u00ed\u0165ov\u00fd z\u00e1sobn\u00edk. M\u016f\u017ee b\u00fdt rovn\u011b\u017e nutn\u00fd samostatn\u00fd gener\u00e1tor paket\u016f a server pro p\u0159\u00edjem odpov\u011bd\u00ed. <\/p>\n

Plnohodnotn\u00fd simul\u00e1tor vytv\u00e1\u0159\u00ed prost\u0159ed\u00ed pro spu\u0161t\u011bn\u00ed cel\u00e9ho softwarov\u00e9ho z\u00e1sobn\u00edku, kter\u00fd zahrnuje v\u0161echno, po\u010d\u00ednaje BIOS a bootloaderem a\u017e po samotn\u00fd opera\u010dn\u00ed syst\u00e9m a r\u016fzn\u00e9 jeho podsystemy, jako je zm\u00edn\u011bn\u00fd s\u00ed\u0165ov\u00fd z\u00e1sobn\u00edk, ovlada\u010de a aplikace na \u00farovni u\u017eivatele. K tomu je v n\u011bm implementov\u00e1no softwarov\u00e9 modelov\u00e1n\u00ed v\u011bt\u0161iny za\u0159\u00edzen\u00ed po\u010d\u00edta\u010de: procesor a pam\u011b\u0165, disk, vstupn\u011b-v\u00fdstupn\u00ed za\u0159\u00edzen\u00ed (kl\u00e1vesnice, my\u0161, displej), jako\u017e i samotn\u00e1 s\u00ed\u0165ov\u00e1 karta. <\/p>\n

N\u00ed\u017ee je uveden blokov\u00fd diagram \u010dipov\u00e9 sady x58 od spole\u010dnosti Intel. V plnoplo\u0161n\u00e9 simulaci po\u010d\u00edta\u010de na t\u00e9to \u010dipov\u00e9 sad\u011b je nutn\u00e9 realizovat v\u011bt\u0161inu z uveden\u00fdch za\u0159\u00edzen\u00ed, v\u010detn\u011b t\u011bch, kter\u00e9 se nach\u00e1zej\u00ed uvnit\u0159 IOH (Input\/Output Hub) a ICH (Input\/Output Controller Hub), ale kter\u00e9 nejsou na blokov\u00e9m diagramu podrobn\u011b nakresleny. I kdy\u017e, jak ukazuje praxe, existuje pom\u011brn\u011b m\u00e1lo za\u0159\u00edzen\u00ed, kter\u00e1 nejsou pou\u017eita softwarem, kter\u00fd hodl\u00e1me spustit. Modely takov\u00fdch za\u0159\u00edzen\u00ed nen\u00ed nutn\u00e9 vytv\u00e1\u0159et. <\/p>\n

\"Simul\u00e1tory
\n
\nNej\u010dast\u011bji se plnoplo\u0161n\u00e9 simul\u00e1tory realizuj\u00ed na \u00farovni instrukc\u00ed procesoru (ISA, viz p\u0159edchoz\u00ed \u010dl\u00e1nek<\/a><\/noindex>). To umo\u017e\u0148uje relativn\u011b rychle a levn\u011b vytvo\u0159it samotn\u00fd simul\u00e1tor. \u00darove\u0148 ISA je tak\u00e9 dobr\u00e1 v tom, \u017ee z\u016fst\u00e1v\u00e1 v\u00edce \u010di m\u00e9n\u011b konstantn\u00ed, na rozd\u00edl od nap\u0159\u00edklad \u00farovn\u011b API\/ABI, kter\u00e1 se m\u011bn\u00ed \u010dast\u011bji. Krom\u011b toho realizace na \u00farovni instrukc\u00ed umo\u017e\u0148uje spou\u0161t\u011bt takzvan\u00fd nemodifikovan\u00fd bin\u00e1rn\u00ed software, to znamen\u00e1 spou\u0161t\u011bt ji\u017e zkompilovan\u00fd k\u00f3d bez jak\u00fdchkoliv zm\u011bn, p\u0159esn\u011b v t\u00e9 podob\u011b, jak je pou\u017e\u00edv\u00e1n na re\u00e1ln\u00e9m hardwaru. Jin\u00fdmi slovy, m\u016f\u017eete vytvo\u0159it kopii (\u201edump\u201c) pevn\u00e9ho disku, uv\u00e9st jej jako obraz pro model v plnoplo\u0161n\u00e9m simul\u00e1toru a \u2013 voil\u00e0! \u2013 opera\u010dn\u00ed syst\u00e9m a dal\u0161\u00ed programy se na\u010dtou v simul\u00e1toru bez jak\u00fdchkoli dal\u0161\u00edch akc\u00ed. <\/p>\n

V\u00fdkon simul\u00e1tor\u016f <\/h3>\n

\"Simul\u00e1tory
\n
\nJak bylo ji\u017e zm\u00edn\u011bno, samotn\u00fd proces simulace cel\u00e9ho syst\u00e9mu, tedy v\u0161ech jeho za\u0159\u00edzen\u00ed, je pom\u011brn\u011b pomal\u00fd. Pokud nav\u00edc realizujete v\u0161e na velmi detailn\u00ed \u00farovni, nap\u0159\u00edklad mikroarchitektonick\u00e9 nebo logick\u00e9, pak se v\u00fdkon stane extr\u00e9mn\u011b pomal\u00fdm. \u00darove\u0148 instrukc\u00ed je v\u0161ak vhodn\u00fdm v\u00fdb\u011brem a umo\u017e\u0148uje opera\u010dn\u00edm syst\u00e9m\u016fm a program\u016fm b\u011b\u017eet rychlostmi, kter\u00e9 jsou pro u\u017eivatele dostate\u010dn\u00e9 pro pohodlnou interakci s nimi. <\/p>\n

Zde je vhodn\u00e9 se dotknout t\u00e9matu v\u00fdkonu simul\u00e1tor\u016f. Obvykle se m\u011b\u0159\u00ed v IPS (instrukce za sekundu), p\u0159esn\u011bji v MIPS (miliony IPS), tedy v po\u010dtu instrukt\u00e1\u017e\u00ed procesoru proveden\u00fdch simul\u00e1torem za jednu sekundu. Z\u00e1rove\u0148 v\u0161ak rychlost simulace z\u00e1vis\u00ed tak\u00e9 na v\u00fdkonu syst\u00e9mu, na kter\u00e9m samotn\u00e1 simulace b\u011b\u017e\u00ed. Proto by bylo mo\u017en\u00e1 spr\u00e1vn\u011bj\u0161\u00ed mluvit o \u201ezpomalov\u00e1n\u00ed\u201c (slowdown) simul\u00e1toru ve srovn\u00e1n\u00ed s p\u016fvodn\u00edm syst\u00e9mem. <\/p>\n

Nejb\u011b\u017en\u011bj\u0161\u00ed plnohodnotn\u00e9 simul\u00e1tory na trhu, jako jsou QEMU, VirtualBox nebo VmWare Workstation, maj\u00ed dobrou v\u00fdkonnost. Pro u\u017eivatele m\u016f\u017ee b\u00fdt t\u00e9m\u011b\u0159 nepost\u0159ehnuteln\u00e9, \u017ee pr\u00e1ce prob\u00edh\u00e1 v simul\u00e1toru. K tomu p\u0159isp\u00edv\u00e1 speci\u00e1ln\u00ed schopnost virtualizace implementovan\u00e1 v procesorech, algoritmy bin\u00e1rn\u00ed translace a dal\u0161\u00ed zaj\u00edmav\u00e9 aspekty. To je v\u0161e t\u00e9ma pro samostatn\u00fd \u010dl\u00e1nek, ale pokud bychom to m\u011bli shrnout, virtualizace je hardwarov\u00e1 schopnost modern\u00edch procesor\u016f, kter\u00e1 umo\u017e\u0148uje simul\u00e1tor\u016fm neprov\u00e1d\u011bt simulaci instrukc\u00ed, ale p\u0159ed\u00e1vat je p\u0159\u00edmo k vykon\u00e1n\u00ed do skute\u010dn\u00e9ho procesoru, pokud se samoz\u0159ejm\u011b architektury simul\u00e1toru a procesoru shoduj\u00ed. Bin\u00e1rn\u00ed translace je p\u0159eklad k\u00f3du hostitelsk\u00e9 strojov\u00e9 architektury do k\u00f3du c\u00edlov\u00e9ho a jeho n\u00e1sledn\u00e9 vykon\u00e1n\u00ed na skute\u010dn\u00e9m procesoru. V\u00fdsledkem je, \u017ee simulace je jenom o n\u011bco pomalej\u0161\u00ed, p\u0159ibli\u017en\u011b 5-10kr\u00e1t, a \u010dasto dokonce b\u011b\u017e\u00ed se stejnou rychlost\u00ed jako skute\u010dn\u00fd syst\u00e9m. Na to v\u0161ak m\u00e1 vliv mnoho faktor\u016f. Nap\u0159\u00edklad, pokud chceme simulovat syst\u00e9m s n\u011bkolika des\u00edtkami procesor\u016f, rychlost se okam\u017eit\u011b sn\u00ed\u017e\u00ed na n\u011bkolik des\u00edtekkr\u00e1t. Na druhou stranu, simul\u00e1tory jako Simics v posledn\u00edch verz\u00edch podporuj\u00ed v\u00edcej\u00e1drov\u00fd hostitelsk\u00fd hardware a efektivn\u011b paralelizuj\u00ed simulovan\u00e9 j\u00e1dra na j\u00e1dra skute\u010dn\u00e9ho procesoru. <\/p>\n

Pokud jde o rychlost mikroarchitektonick\u00e9 simulace, je obvykle o n\u011bkolik \u0159\u00e1d\u016f pomalej\u0161\u00ed, p\u0159ibli\u017en\u011b 1000-10000kr\u00e1t, ne\u017e vykon\u00e1n\u00ed na b\u011b\u017en\u00e9m po\u010d\u00edta\u010di bez simulace. A implementace na \u00farovni logick\u00fdch prvk\u016f jsou je\u0161t\u011b o n\u011bkolik \u0159\u00e1d\u016f pomalej\u0161\u00ed. Proto se jako emul\u00e1tor na t\u00e9to \u00farovni pou\u017e\u00edvaj\u00ed FPGA, co\u017e v\u00fdrazn\u011b zvy\u0161uje v\u00fdkonnost. <\/p>\n

Graf n\u00ed\u017ee ukazuje p\u0159ibli\u017enou z\u00e1vislost rychlosti simulace na detailech modelu. <\/p>\n

\"Simul\u00e1tory
\n<\/p>\n

Ciklov\u00e1 simulace <\/h3>\n

\nA\u010dkoli maj\u00ed mikroarchitektonick\u00e9 simul\u00e1tory n\u00edzkou rychlost prov\u00e1d\u011bn\u00ed, jsou pom\u011brn\u011b roz\u0161\u00ed\u0159en\u00e9. Modelov\u00e1n\u00ed intern\u00edch blok\u016f procesoru je nezbytn\u00e9 k p\u0159esn\u00e9 simulaci doby prov\u00e1d\u011bn\u00ed ka\u017ed\u00e9 instrukce. M\u016f\u017ee doj\u00edt k nedorozum\u011bn\u00ed \u2013 proto\u017ee se m\u016f\u017ee zd\u00e1t, pro\u010d jednodu\u0161e nezprogramovat dobu prov\u00e1d\u011bn\u00ed pro ka\u017edou instrukci. Takov\u00fd simul\u00e1tor by v\u0161ak pracoval velmi nep\u0159esn\u011b, proto\u017ee doba prov\u00e1d\u011bn\u00ed stejn\u00e9 instrukce se m\u016f\u017ee li\u0161it mezi jednotliv\u00fdmi vyvol\u00e1n\u00edmi. <\/p>\n

Prvn\u00edm p\u0159\u00edkladem je instrukce p\u0159\u00edstupu do pam\u011bti. Pokud je po\u017eadovan\u00e1 bu\u0148ka pam\u011bti dostupn\u00e1 v cache, doba prov\u00e1d\u011bn\u00ed bude minim\u00e1ln\u00ed. Pokud dan\u00e9 informace v cache nejsou (\"cache miss\"), v\u00fdrazn\u011b to prodlou\u017e\u00ed dobu prov\u00e1d\u011bn\u00ed instrukce. Proto je pro p\u0159esnou simulaci nezbytn\u00fd model cache. Nicm\u00e9n\u011b model cache to nen\u00ed. Procesor nebude prost\u011b \u010dekat na z\u00edsk\u00e1n\u00ed dat z pam\u011bti, pokud nejsou v cache. M\u00edsto toho za\u010dne prov\u00e1d\u011bt n\u00e1sleduj\u00edc\u00ed instrukce, vyb\u00edr\u00e1 ty, kter\u00e9 nejsou z\u00e1visl\u00e9 na v\u00fdsledku \u010dten\u00ed z pam\u011bti. Toto se naz\u00fdv\u00e1 prov\u00e1d\u011bn\u00ed \"mimo po\u0159ad\u00ed\" (OOO, out of order execution), kter\u00e9 je nezbytn\u00e9 k minimalizaci doby ne\u010dinnosti procesoru. Zohledn\u011bn\u00ed v\u0161eho tohoto p\u0159i v\u00fdpo\u010dtu doby prov\u00e1d\u011bn\u00ed instrukc\u00ed napom\u016f\u017ee simulace odpov\u00eddaj\u00edc\u00edch blok\u016f procesoru. Mezi t\u011bmito instrukcemi, kter\u00e9 se prov\u00e1d\u011bj\u00ed, zat\u00edmco se \u010dek\u00e1 na v\u00fdsledek \u010dten\u00ed z pam\u011bti, m\u016f\u017ee b\u00fdt i podm\u00edn\u011bn\u00fd skok. Pokud v\u00fdsledek podm\u00ednky nen\u00ed v sou\u010dasnosti zn\u00e1m\u00fd, procesor op\u011bt nezastav\u00ed prov\u00e1d\u011bn\u00ed, ale ud\u011bl\u00e1 \"p\u0159edpoklad\", prov\u00e1d\u00ed p\u0159\u00edslu\u0161n\u00fd skok a pokra\u010duje preventivn\u011b v prov\u00e1d\u011bn\u00ed instrukc\u00ed od m\u00edsta skoku. Tento blok, naz\u00fdvan\u00fd branch predictor, by m\u011bl b\u00fdt rovn\u011b\u017e implementov\u00e1n v mikroarchitektonick\u00e9m simul\u00e1toru. <\/p>\n

Obr\u00e1zek n\u00ed\u017ee ukazuje hlavn\u00ed bloky procesoru, jejich znalost nen\u00ed nezbytn\u00e1, je uvedena pouze k tomu, aby uk\u00e1zala slo\u017eitost mikroarchitektonick\u00e9 realizace. <\/p>\n

\"Simul\u00e1tory
\n
\nPr\u00e1ce v\u0161ech t\u011bchto blok\u016f v re\u00e1ln\u00e9m procesoru je synchronizov\u00e1na pomoc\u00ed speci\u00e1ln\u00edch taktov\u00fdch sign\u00e1l\u016f, podobn\u011b jako u modelu. Takov\u00e9mu mikroarchitektonick\u00e9mu simul\u00e1toru se \u0159\u00edk\u00e1 cyklick\u00fd (cycle accurate). Jeho hlavn\u00edm \u00fa\u010delem je p\u0159esn\u011b p\u0159edpov\u011bd\u011bt v\u00fdkon vyv\u00edjen\u00e9ho procesoru a\/nebo spo\u010d\u00edtat \u010das prov\u00e1d\u011bn\u00ed ur\u010dit\u00e9ho programu, nap\u0159\u00edklad n\u011bjak\u00e9ho benchmarku. Pokud budou hodnoty ni\u017e\u0161\u00ed ne\u017e pot\u0159ebn\u00e9, bude t\u0159eba upravit algoritmy a bloky procesoru nebo optimalizovat program. <\/p>\n

Jak bylo uvedeno v\u00fd\u0161e, cyklick\u00e1 simulace je velmi pomal\u00e1, a proto se pou\u017e\u00edv\u00e1 pouze p\u0159i zkoum\u00e1n\u00ed ur\u010dit\u00fdch aspekt\u016f pr\u00e1ce programu, kde je nutn\u00e9 zjistit skute\u010dnou rychlost prov\u00e1d\u011bn\u00ed program\u016f a posoudit budouc\u00ed v\u00fdkon za\u0159\u00edzen\u00ed, jeho\u017e prototyp je modelov\u00e1n. <\/p>\n

P\u0159itom pro simulaci zbyl\u00e9ho \u010dasu pr\u00e1ce programu je pou\u017eit funk\u010dn\u00ed simul\u00e1tor. Jak prob\u00edh\u00e1 takov\u00e9 kombinovan\u00e9 pou\u017eit\u00ed v re\u00e1ln\u00e9m \u017eivot\u011b? Nejprve se spust\u00ed funk\u010dn\u00ed simul\u00e1tor, na kter\u00e9m se na\u010dte opera\u010dn\u00ed syst\u00e9m a v\u0161e pot\u0159ebn\u00e9 pro spu\u0161t\u011bn\u00ed zkouman\u00e9ho programu. Nezaj\u00edm\u00e1 n\u00e1s ani samotn\u00fd opera\u010dn\u00ed syst\u00e9m, ani po\u010d\u00e1te\u010dn\u00ed f\u00e1ze spu\u0161t\u011bn\u00ed programu, jeho konfigurace a podobn\u011b. Ov\u0161em ani tyto \u010d\u00e1sti nem\u016f\u017eeme p\u0159esko\u010dit a okam\u017eit\u011b p\u0159ej\u00edt k prov\u00e1d\u011bn\u00ed programu od poloviny. Proto jsou v\u0161echny tyto p\u0159edb\u011b\u017en\u00e9 f\u00e1ze provozov\u00e1ny na funk\u010dn\u00edm simul\u00e1toru. Jakmile program dos\u00e1hne zaj\u00edmav\u00e9ho okam\u017eiku, existuj\u00ed dv\u011b mo\u017enosti. M\u016f\u017eeme model vym\u011bnit za cyklick\u00fd a pokra\u010dovat v prov\u00e1d\u011bn\u00ed. Re\u017eimu simulace, p\u0159i kter\u00e9m se pou\u017e\u00edv\u00e1 prov\u00e1d\u011bn\u00fd k\u00f3d (tj. b\u011b\u017en\u00e9 zkompilovan\u00e9 soubory program\u016f), se \u0159\u00edk\u00e1 simulace podle proveden\u00ed (execution driven simulation). To je nejb\u011b\u017en\u011bj\u0161\u00ed forma simulace. Je tak\u00e9 mo\u017en\u00fd jin\u00fd p\u0159\u00edstup \u2013 simulace na z\u00e1klad\u011b stop (trace driven simulation). <\/p>\n

Simulace na z\u00e1klad\u011b stop <\/h3>\n

\nSkl\u00e1d\u00e1 se ze dvou krok\u016f. Pomoc\u00ed funk\u010dn\u00edho simul\u00e1toru nebo na re\u00e1ln\u00e9m syst\u00e9mu se shrom\u00e1\u017ed\u00ed a zap\u00ed\u0161e do souboru z\u00e1znam \u010dinnost\u00ed programu. Tento z\u00e1znam se naz\u00fdv\u00e1 stopa (trace). V z\u00e1vislosti na tom, co se zkoum\u00e1, m\u016f\u017ee stopa zahrnovat prov\u00e1d\u011bn\u00e9 instrukce, adresy pam\u011bti, \u010d\u00edsla port\u016f, informace o p\u0159eru\u0161en\u00ed. <\/p>\n

Dal\u0161\u00edm krokem je \u201ep\u0159ehr\u00e1n\u00ed\u201c stopy, kdy cyklick\u00fd simul\u00e1tor \u010dte stopu a vykon\u00e1v\u00e1 v\u0161echny pokyny, kter\u00e9 jsou v n\u00ed zaznamen\u00e1ny. Na konci z\u00edsk\u00e1me \u010das vykon\u00e1n\u00ed dan\u00e9ho kusu programu a tak\u00e9 r\u016fzn\u00e9 charakteristiky tohoto procesu, nap\u0159\u00edklad procento z\u00e1sahu do cache. <\/p>\n

D\u016fle\u017eitou vlastnost\u00ed pr\u00e1ce se stopami je determinovanost, tedy \u017ee p\u0159i spu\u0161t\u011bn\u00ed simulace v\u00fd\u0161e uveden\u00fdm zp\u016fsobem opakovan\u011b reprodukujeme stejnou sekvenci akc\u00ed. To n\u00e1m umo\u017e\u0148uje, p\u0159i zm\u011bn\u011b parametr\u016f modelu (velikosti cache, buffer\u016f a front) a pou\u017e\u00edv\u00e1n\u00ed r\u016fzn\u00fdch vnit\u0159n\u00edch algoritm\u016f nebo jejich nastaven\u00ed, prozkoumat, jak\u00fd konkr\u00e9tn\u00ed parametr ovliv\u0148uje v\u00fdkon syst\u00e9mu a kter\u00e1 varianta p\u0159in\u00e1\u0161\u00ed nejlep\u0161\u00ed v\u00fdsledky. To v\u0161e lze prov\u00e9st s modelem prototypu za\u0159\u00edzen\u00ed p\u0159ed vytvo\u0159en\u00edm skute\u010dn\u00e9ho hardwarov\u00e9ho prototypu. <\/p>\n

Slo\u017eitost tohoto p\u0159\u00edstupu spo\u010d\u00edv\u00e1 v nutnosti p\u0159edchoz\u00edho b\u011bhu aplikace a sb\u011bru stopy, stejn\u011b jako obrovsk\u00e9 velikosti souboru se stopou. Mezi v\u00fdhody pat\u0159\u00ed to, \u017ee sta\u010d\u00ed modelovat pouze tu zaj\u00edmavou \u010d\u00e1st za\u0159\u00edzen\u00ed nebo platformy, zat\u00edmco simulace vykon\u00e1n\u00ed obvykle vy\u017eaduje kompletn\u00ed model. <\/p>\n

Tak\u017ee v tomto \u010dl\u00e1nku jsme se pod\u00edvali na zvl\u00e1\u0161tnosti plnohodnotn\u00e9 platformov\u00e9 simulace, hovo\u0159ili jsme o rychlosti implementac\u00ed na r\u016fzn\u00fdch \u00farovn\u00edch, cyklick\u00e9 simulaci a stop\u00e1ch. V dal\u0161\u00edm \u010dl\u00e1nku pop\u00ed\u0161u hlavn\u00ed sc\u00e9n\u00e1\u0159e pou\u017eit\u00ed simul\u00e1tor\u016f, jak pro osobn\u00ed \u00fa\u010dely, tak z pohledu v\u00fdvoje ve velk\u00fdch spole\u010dnostech.
\n
Zdroj: habr.com<\/a> <\/p>","protected":false,"gt_translate_keys":[{"key":"rendered","format":"html"}]},"excerpt":{"rendered":"

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