{"id":103860,"date":"2022-04-23T21:36:37","date_gmt":"2022-04-23T19:36:38","guid":{"rendered":"https:\/\/prohoster.info\/blog\/novosti-interneta\/proekt-verigpu-razvivaet-otkrytyj-gpu-na-yazyke-verilog"},"modified":"2022-04-23T21:36:37","modified_gmt":"2022-04-23T19:36:38","slug":"proekt-verigpu-razvivaet-otkrytyj-gpu-na-yazyke-verilog","status":"publish","type":"post","link":"https:\/\/prohoster.info\/da\/blog\/news\/proekt-verigpu-razvivaet-otkrytyj-gpu-na-yazyke-verilog","title":{"rendered":"VeriGPU-projektet udvikler en \u00e5ben GPU baseret p\u00e5 Verilog.","gt_translate_keys":[{"key":"rendered","format":"text"}]},"content":{"rendered":"

VeriGPU-projektet sigter mod at skabe et \u00e5bent GPU, der udvikles p\u00e5 beskrivelses- og modelleringssproget Verilog. Projektet udvikles oprindeligt ved hj\u00e6lp af Verilog-simulatoren, men n\u00e5r det er klar, vil det kunne bruges til produktion af virkelige chips. Projektets resultater distribueres under MIT-licensen. <\/p>\n

VeriGPU positionerer sig som en specialiseret processor (ASIC), optimeret til at accelerere beregninger relateret til machine learning-systemer. I planerne n\u00e6vnes det at sikre kompatibilitet med deep learning-rammev\u00e6rket PyTorch og implementere muligheder for udvikling af applikationer til VeriGPU ved hj\u00e6lp af HIP (Heterogeneous-Compute Interface) API. Fremadskuende udelukkes ikke tilf\u00f8jelse af st\u00f8tte til andre API'er som SYCL og NVIDIA CUDA. <\/p>\n

GPU'en udvikles baseret p\u00e5 RISC-V instruktion s\u00e6ttet, men den endelige interne arkitektur af GPU-instruktionss\u00e6ttet er svagt kompatibel med RISC-V ISA, da hvis designet af GPU'en ikke passer ind i RISC-V's forst\u00e5else, er der ikke noget krav om at opretholde kompatibilitet med RISC-V. Udviklingen fokuserer p\u00e5 de funktioner, der er n\u00f8dvendige for machine learning-systemer, s\u00e5 der bruges kun BF16 formatet til flydende beregninger for at reducere st\u00f8rrelsen og kompleksiteten af chipmatrixen, og kun de mest efterspurgte flydende operationer til machine learning er tilg\u00e6ngelige, s\u00e5som exp, log, tanh og sqrt. <\/p>\n

Af de allerede tilg\u00e6ngelige komponenter n\u00e6vnes GPU-controller, APU (Accelerated Processing Unit) til heltalsoperationer («+»,»-«,»\\\/»,»*»), en enhed til flydende punkt operationer («+»,»*») og en enhed til forgrening. Til udvikling af applikationer tilbydes assembler og underst\u00f8ttelse af kompilering af kode i C++ baseret p\u00e5 LLVM. Blandt de planlagte funktioner fremh\u00e6ves parallel udf\u00f8relse af instruktioner, caching af data- og instruktionshukommelse samt SIMT-operationer (Single instruction multiple thread).

\"VeriGPU-projektet<\/center>
\n
Kilde: opennet.ru<\/a> <\/p>","protected":false,"gt_translate_keys":[{"key":"rendered","format":"html"}]},"excerpt":{"rendered":"

\u041f\u0440\u043e\u0435\u043a\u0442 VeriGPU \u043d\u0430\u0446\u0435\u043b\u0435\u043d \u043d\u0430 \u0441\u043e\u0437\u0434\u0430\u043d\u0438\u0435 \u043e\u0442\u043a\u0440\u044b\u0442\u043e\u0433\u043e GPU, \u0440\u0430\u0437\u0432\u0438\u0432\u0430\u0435\u043c\u043e\u0433\u043e \u043d\u0430 \u044f\u0437\u044b\u043a\u0435 \u043e\u043f\u0438\u0441\u0430\u043d\u0438\u044f \u0438 \u043c\u043e\u0434\u0435\u043b\u0438\u0440\u043e\u0432\u0430\u043d\u0438\u044f \u044d\u043b\u0435\u043a\u0442\u0440\u043e\u043d\u043d\u044b\u0445 \u0441\u0438\u0441\u0442\u0435\u043c Verilog. \u0418\u0437\u043d\u0430\u0447\u0430\u043b\u044c\u043d\u043e \u043f\u0440\u043e\u0435\u043a\u0442 \u0440\u0430\u0437\u0440\u0430\u0431\u0430\u0442\u044b\u0432\u0430\u0435\u0442\u0441\u044f \u0441 \u0438\u0441\u043f\u043e\u043b\u044c\u0437\u043e\u0432\u0430\u043d\u0438\u0435\u043c \u0441\u0438\u043c\u0443\u043b\u044f\u0442\u043e\u0440\u0430 Verilog, \u043d\u043e \u043f\u043e\u0441\u043b\u0435 \u0434\u043e\u0432\u0435\u0434\u0435\u043d\u0438\u044f \u0434\u043e \u0433\u043e\u0442\u043e\u0432\u043d\u043e\u0441\u0442\u0438 \u0441\u043c\u043e\u0436\u0435\u0442 \u0438\u0441\u043f\u043e\u043b\u044c\u0437\u043e\u0432\u0430\u0442\u044c\u0441\u044f \u0434\u043b\u044f \u043f\u0440\u043e\u0438\u0437\u0432\u043e\u0434\u0441\u0442\u0432\u0430 \u0440\u0435\u0430\u043b\u044c\u043d\u044b\u0445 \u0447\u0438\u043f\u043e\u0432. \u041d\u0430\u0440\u0430\u0431\u043e\u0442\u043a\u0438 \u043f\u0440\u043e\u0435\u043a\u0442\u0430 \u0440\u0430\u0441\u043f\u0440\u043e\u0441\u0442\u0440\u0430\u043d\u044f\u044e\u0442\u0441\u044f \u043f\u043e\u0434 \u043b\u0438\u0446\u0435\u043d\u0437\u0438\u0435\u0439 MIT. VeriGPU \u043f\u043e\u0437\u0438\u0446\u0438\u043e\u043d\u0438\u0440\u0443\u0435\u0442\u0441\u044f \u043a\u0430\u043a \u0441\u043f\u0435\u0446\u0438\u0430\u043b\u0438\u0437\u0438\u0440\u043e\u0432\u0430\u043d\u043d\u044b\u0439 \u043f\u0440\u043e\u0446\u0435\u0441\u0441\u043e\u0440 (ASIC), \u043e\u043f\u0442\u0438\u043c\u0438\u0437\u0438\u0440\u043e\u0432\u0430\u043d\u043d\u044b\u0439 \u0434\u043b\u044f \u0443\u0441\u043a\u043e\u0440\u0435\u043d\u0438\u044f \u0432\u044b\u0447\u0438\u0441\u043b\u0435\u043d\u0438\u0439, \u0441\u0432\u044f\u0437\u0430\u043d\u043d\u044b\u0445 \u0441 \u0441\u0438\u0441\u0442\u0435\u043c\u0430\u043c\u0438 \u043c\u0430\u0448\u0438\u043d\u043d\u043e\u0433\u043e \u043e\u0431\u0443\u0447\u0435\u043d\u0438\u044f. […]<\/p>\n","protected":false,"gt_translate_keys":[{"key":"rendered","format":"html"}]},"author":1,"featured_media":103861,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[702],"tags":[],"class_list":["post-103860","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-news"],"aioseo_notices":[],"aioseo_head":"\n\t\t\n\t\n\t\n\t\n\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\n","aioseo_head_json":{"title":"\ud83e\udd47VeriGPU-projektet udvikler et \u00e5bent GPU p\u00e5 Verilog-sproget | ProHoster","description":"VeriGPU-projektet sigter mod at skabe et \u00e5bent GPU, der udvikles p\u00e5 beskrivelses- og modelleringssproget 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