{"id":30179,"date":"2019-10-31T21:34:00","date_gmt":"2019-10-31T18:34:00","guid":{"rendered":"https:\/\/prohoster.info\/blog\/asic-dlya-mashinnogo-obucheniya-dolzhny-proektirovatsya-avtomaticheski\/"},"modified":"2019-10-31T21:34:00","modified_gmt":"2019-10-31T18:34:00","slug":"asic-dlya-mashinnogo-obucheniya-dolzhny-proektirovatsya-avtomaticheski","status":"publish","type":"post","link":"https:\/\/prohoster.info\/da\/blog\/asic-dlya-mashinnogo-obucheniya-dolzhny-proektirovatsya-avtomaticheski","title":{"rendered":"ASIC til maskinl\u00e6ring b\u00f8r designes automatisk.","gt_translate_keys":[{"key":"rendered","format":"text"}]},"content":{"rendered":"

Det er n\u00e6ppe nogen, der vil bestride, at design af skr\u00e6ddersyede ASIC-chips ikke er en simpel og hurtig proces. Man \u00f8nsker og har brug for, at det g\u00e5r hurtigere: i dag afleveres algoritmen, og om en uge hentes det f\u00e6rdige digitale projekt. Problemet er, at meget specialiserede ASICs n\u00e6sten er h\u00e5ndlavede produkter. De er sj\u00e6ldent n\u00f8dvendige i millionvis, hvor man kan bruge ubegr\u00e6nsede ressourcer i tid og penge, hvis det skal g\u00f8res hurtigt. Specialiserede ASICs, som derfor er mest effektive til at l\u00f8se specifikke opgaver, b\u00f8r kunne udvikles billigere, hvilket er megaaktuelt i den nuv\u00e6rende fase af udviklingen inden for maskinl\u00e6ring. P\u00e5 denne front kan man ikke l\u00e6ngere klare sig med det bagage, der er opbygget af computerindustrien, og is\u00e6r med de gennembrud, som GPU'erne har givet inden for maskinl\u00e6ring (ML).<\/p>\n

\"ASIC<\/p>\n

For at fremskynde designet af ASICs til ML-opgaver etablerer DARPA et nyt program - Real Time Machine Learning (RTML). Programmet for realtids maskinl\u00e6ring har til form\u00e5l at udvikle en compiler eller softwareplatform, der automatisk kan designe chiparkitekturen til et specifikt ML-rammev\u00e6rk. Platformen skal automatisk analysere den foresl\u00e5ede maskinl\u00e6ringsalgoritme og datas\u00e6ttet til tr\u00e6ning af denne algoritme og skal derefter generere kode til oprettelse af specialiserede ASICs p\u00e5 Verilog. Specialister inden for algoritmeudvikling til ML har ikke den n\u00f8dvendige viden om chipdesign, mens chipdesignere sj\u00e6ldent er bekendt med principperne for maskinl\u00e6ring. RTML-programmet skal hj\u00e6lpe med at kombinere fordelene fra begge sider i en automatiseret platform til udvikling af ASICs til maskinl\u00e6ring.<\/p>\n

I l\u00f8bet af programmets RTML livscyklus skal de fundne l\u00f8sninger testes inden for to hovedomr\u00e5der: drift i 5G-netv\u00e6rk og billedbehandling. Programmet RTML og de opbyggede softwareplatforme til automatisk design af ML-acceleratorer vil ogs\u00e5 blive brugt til udvikling og test af nye ML-algoritmer og datas\u00e6t. Derved kan potentialet for nye rammer vurderes, inden 'silicium' designet p\u00e5begyndes. DARPA's partner i RTML-programmet er National Science Foundation (NSF), som ogs\u00e5 arbejder med maskinl\u00e6ring og udvikling af ML-algoritmer. Den udviklede compiler vil blive overdraget til NSF, mens DARPA forventer at modtage en compiler og en platform til design af ML-algoritmer tilbage. Fremover vil hardwaredesign og algoritmeudvikling v\u00e6re et integreret l\u00f8sninger, hvilket vil f\u00f8re til fremkomsten af selvuddannende realtids maskinsystemer.<\/p>\n

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Kilde: 3dnews.ru<\/a><\/p>","protected":false,"gt_translate_keys":[{"key":"rendered","format":"html"}]},"excerpt":{"rendered":"

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