{"id":33621,"date":"2019-10-31T21:53:47","date_gmt":"2019-10-31T18:53:47","guid":{"rendered":"https:\/\/prohoster.info\/blog\/additional-uplinks-v-arhitekture-sistemnoj-logiki-intel-c620\/"},"modified":"2019-10-31T21:53:47","modified_gmt":"2019-10-31T18:53:47","slug":"additional-uplinks-v-arhitekture-sistemnoj-logiki-intel-c620","status":"publish","type":"post","link":"https:\/\/prohoster.info\/da\/blog\/administrirovanie\/additional-uplinks-v-arhitekture-sistemnoj-logiki-intel-c620","title":{"rendered":"Yderligere opkoblinger i arkitekturen af Intel C620 systemlogik","gt_translate_keys":[{"key":"rendered","format":"text"}]},"content":{"rendered":"

I x86-arkitektur er der opst\u00e5et to str\u00f8mninger, der supplerer hinanden. If\u00f8lge den ene version skal man bev\u00e6ge sig mod integrationen af beregnings- og styresystemressourcer i \u00e9n enkelt chip. Den anden tilgang fremmer fordelingen af ansvar: processoren udstyres med en kraftfuld bus, der danner et periferisk, skalerbart \u00f8kosystem. Dette danner grundlaget for topologien af Intels C620-systemlogik til h\u00f8jere niveau platforme.<\/a><\/noindex><\/p>\n

Den v\u00e6sentligste forskel fra den tidligere Intel C610-chips\u00e6t er udvidelsen af kommunikationskanalen mellem processoren og de perifere enheder, der indg\u00e5r i PCH-chippen, ved brug af PCIe-links sammen med den traditionelle DMI-bus.<\/p>\n

\"Yderligere
\n
\nLad os se n\u00e6rmere p\u00e5 nyhederne inden for Intel Lewisburg\u2019 sydlige bro: hvilke evolution\u00e6re og revolution\u00e6re tilgange har udvidet dens bef\u00f8jelser i kommunikationen med processorerne?<\/p>\n

Evolution\u00e6re \u00e6ndringer i kommunikationen mellem CPU-PCH<\/h2>\n

\nI den evolution\u00e6re tilgang har hovedkommunikationskanalen mellem CPU og den sydlige bro, som er DMI (Direct Media Interface) busen, f\u00e5et st\u00f8tte til PCIe x4 Gen3 tilstand med en ydeevne p\u00e5 8.0 GT\/S. Tidligere, i Intel C610 PCH, blev kommunikationen mellem processoren og systemlogikken udf\u00f8rt i PCIe x4 Gen 2 tilstand med en b\u00e5ndbredde p\u00e5 5.0 GT\/S.<\/p>\n

\"Yderligere
\n
\nSammenligning af funktionaliteten mellem systemlogikken Intel C610 og C620<\/em><\/p>\n

Vi bem\u00e6rker, at dette undersystem er betydeligt mere konservativt end de indbyggede PCIe-porte i processoren, der normalt bruges til tilslutning af GPU'er og NVMe-lagringsenheder, hvor PCIe 3.0 allerede l\u00e6nge har v\u00e6ret i brug, og der foresl\u00e5s et skift til PCI Express Gen4.<\/p>\n

Revolutionerende \u00e6ndringer i kommunikationen mellem CPU-PCH<\/h2>\n

\nRevolution\u00e6re \u00e6ndringer inkluderer tilf\u00f8jelsen af nye PCIe-kanaler til kommunikationen mellem CPU og PCH, kaldet Additional Uplinks. Fysisk set er det to PCI Express-porte, der fungerer i PCIe x8 Gen3 og PCIe x16 Gen3 tilstande, begge ved 8.0 GT\/S.<\/p>\n

\"Yderligere
\n
\nTil interaktion mellem CPU og Intel C620 PCH bruges 3 busser: DMI og to PCI Express-porte.<\/em><\/p>\n

Hvorfor var det n\u00f8dvendigt at revidere den eksisterende kommunikationstopologi med Intel C620? For det f\u00f8rste kan der integreres op til 4 netv\u00e6rkscontrollere 10GbE med RDMA-funktionalitet i PCH. For det andet st\u00e5r et nyt og hurtigere generation af Intel QuickAssist Technology (QAT)-co-processorer for kryptering af netv\u00e6rkstrafik og udveksling med lagersystemet, som giver hardwareunderst\u00f8ttelse af kompression og kryptering. Og endelig er \"innovationsmotoren\" - Innovation Engine<\/a><\/noindex>, som kun vil v\u00e6re tilg\u00e6ngelig for OEM-producenter.<\/p>\n

Skalerbarhed og fleksibilitet<\/h2>\n

\nEn vigtig egenskab er muligheden for valg af ikke kun PCH-forbindelsestopologi, men ogs\u00e5 prioriteringer af interne ressourcer i chippen til adgang til hurtige forbindelser med centralprocessor(en). Desuden, i en s\u00e6rlig EPO-tilstand (EndPoint Only Mode), forbindes PCH i status som en almindelig PCI Express-enhed, der indeholder ressourcer til 10 GbE og Intel QAT. I denne forbindelse er den klassiske DMI-gr\u00e6nseflade samt en r\u00e6kke Legacy-underystemmer, der er vist p\u00e5 diagrammet med sorte farver, deaktiveret.<\/p>\n

\"Yderligere
\n
\nDen interne arkitektur af Intel C620 PCH-chippen<\/em><\/p>\n

Teoretisk set giver dette mulighed for at bruge mere end \u00e9n Intel C620 PCH-chip i systemet, hvilket skalerer funktionaliteten af 10 GbE og Intel QAT i henhold til ydeevnekravene. Legacy-funktioner, der kun er n\u00f8dvendige i \u00e9n enkelt kopi, kan kun aktiveres p\u00e5 en af de installerede PCH-chips.<\/p>\n

S\u00e5ledes vil det endelige ord i designet tilh\u00f8re platformens udvikler, der handler p\u00e5 grundlag af b\u00e5de teknologiske og markedsm\u00e6ssige faktorer i overensstemmelse med positioneringen af hvert enkelt produkt.
\n
Kilde: habr.com<\/a><\/p>","protected":false,"gt_translate_keys":[{"key":"rendered","format":"html"}]},"excerpt":{"rendered":"

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If\u00f8lge en version skal vi bev\u00e6ge os mod integration af beregnings- og styringsressourcer i en enkelt krystall.","canonical_url":"https:\/\/prohoster.info\/da\/blog\/administrirovanie\/additional-uplinks-v-arhitekture-sistemnoj-logiki-intel-c620","robots":"max-image-preview:large","keywords":"","webmasterTools":{"miscellaneous":""},"schema":null,"og:locale":"da_DK","og:site_name":"ProHoster | \u041a\u0443\u043f\u0438\u0442\u044c \u043d\u0430\u0434\u0435\u0436\u043d\u044b\u0439 \u0445\u043e\u0441\u0442\u0438\u043d\u0433 \u0434\u043b\u044f \u0441\u0430\u0439\u0442\u043e\u0432 \u0441 \u0437\u0430\u0449\u0438\u0442\u043e\u0439 \u043e\u0442 DDoS, VPS VDS \u0441\u0435\u0440\u0432\u0435\u0440\u044b","og:type":"article","og:title":"\ud83e\udd47Additional Uplinks \u0432 \u0430\u0440\u0445\u0438\u0442\u0435\u043a\u0442\u0443\u0440\u0435 \u0441\u0438\u0441\u0442\u0435\u043c\u043d\u043e\u0439 \u043b\u043e\u0433\u0438\u043a\u0438 Intel C620 | ProHoster","og:description":"\u0412 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