The Libre-SOC project is developing an open chip with a hybrid architecture based on the CDC 6600 style, where CPU, VPU, and GPU instructions are not separated but offered in a single ISA to reduce the size and complexity of the chip. This project has reached the stage of transferring the first test sample into production. Originally, it was developed under the name Libre RISC-V, but was renamed to Libre-SOC after the decision was made to replace RISC-V with the OpenPOWER 3.0 instruction set architecture (ISA).
The project aims to create a complete, fully open, and royalty-free system on a chip (SoC) that can be used in single-board computers, netbooks, and various portable devices. In addition to the usual CPU instructions and general-purpose registers, Libre-SOC provides capabilities for performing vector operations and specialized computations typical of VPU and GPU all within one functional block. The chip uses the OpenPOWER instruction set architecture, with the Simple-V extension for vectorization and parallel data processing instructions, as well as specialized instructions for converting to ARGB and executing standard 3D operations.
GPU instructions are focused on use with the Vulkan graphic API, while the VPU is aimed at accelerating YUV-RGB conversion and decoding formats such as MPEG1/2, MPEG4 ASP (xvid), H.264, H.265, VP8, VP9, AV1, MP3, AC3, Vorbis, and Opus. A free driver is being developed for Mesa that utilizes Libre-SOC's capabilities to provide hardware-accelerated software implementation of the Vulkan graphic API. For example, Vulkan shaders can be compiled using a JIT engine to execute with the specialized instructions available in Libre-SOC.
The next test prototype plans to implement the SVP64 (Variable-length Vectorisation) extension, allowing Libre-SOC to function as a vector processor (in addition to 32 64-bit general-purpose registers, 128 registers for vector computations will be provided). The first prototype includes a single core operating at a frequency of 300 MHz, but over the next two years, a 4-core version is planned, followed by an 8-core version, and in the long term, a 64-core version.
The first batch of the chip will be produced by TSMC using a 180nm process. All project developments are distributed under open licenses, including GDS-II format files describing the complete chip topology, sufficient for starting your own production. Libre-SOC will be the first fully independent chip based on Power architecture, produced outside of IBM. The development used the hardware description language nMigen (HDL based on Python, without using VHDL and Verilog), FlexLib standard cell libraries from the Chips4Makers project, and the free VLSI toolset Coriolis2 for conversion from HDL to GDS-II.
The development of Libre-SOC was funded by the NLnet Foundation, which allocated 400,000 euros for the creation of a fully open chip as part of a program aimed at creating verifiable and trustworthy fundamental technical solutions. The chip measures 5.5×5.9 mm and includes 130,000 logic gates. It features four 4KB SRAM modules and a 300 MHz phase-locked loop (PLL) block.
Source: opennet.ru
