Google, in collaboration with manufacturing companies SkyWater Technology and Efabless, has launched an initiative that allows open hardware developers to manufacture their developed chips for free. The initiative aims to stimulate the development of open hardware, reduce costs in open project development, and simplify interactions with manufacturing plants. Thanks to this initiative, anyone can start developing their own custom chips without fearing high costs for producing initial prototypes. All expenses for production, packaging, and delivery are covered by Google.
Applications for inclusion in the free manufacturing program can be submitted every two months. The next slot will close on June 8, and the chips that are accepted will be ready by August 30 and sent to the creators on October 18. From the submitted applications, 40 projects will be selected (if there are fewer than 40 applications, all that pass the correctness check will go into production). As a result of the production, the developer will receive 50 chips and 5 boards with the installed chips.
Applications are only accepted from projects that are fully distributed under open licenses, free from non-disclosure agreements (NDA), and not restricting the scope of use of their products. Manufacturing data must be provided in GDSII format, pass the provided test suite, and be reproducible from source design files (i.e., you cannot declare an open project and submit a proprietary layout for production).
To simplify the development of open chips, the following open tools are offered:
- SkyWater PDK (Process Design Kit), a toolkit that describes the manufacturing process used at SkyWater for 130nm (SKY130) and allows the preparation of the necessary design files for chip production.
- OpenLane — a set of components for automating the conversion of RTL circuitry of specialized chips (ASIC) into GDSII format, used in factories for manufacturing chips.
- XLS (Accelerated HW Synthesis) — a toolkit for synthesizing design files with hardware components of chips that correspond to the provided high-level description of the required functionality, structured in a software development style.
- A set of rules for the Bazel build system with support for open tools (Yosys, Verilator, OpenROAD) for working with hardware description languages (Verilog, VHDL, Chisel, nMigen).
- OpenROAD — a framework for automating the development process of open chips.
- Verible — a set of tools for developing in the Verilog language, including a parser, style formatting system, and linter.
Source: opennet.ru
