Few would argue that designing custom ASICs is neither a simple nor a quick process. Yet, there is a desire for speed: today you issue an algorithm, and a week later you pick up the finished digital design. The challenge is that highly specialized ASICs are almost a one-off product. They are rarely needed in millions, where you can spend unlimited money and human resources to complete them quickly. Specialized, and therefore most effective ASICs for their tasks, should be cheaper to develop, which is increasingly relevant at this stage of machine learning development. On this front, one cannot rely solely on the baggage accumulated by the computer market and, in particular, the breakthroughs in GPUs for machine learning (ML).
To accelerate the design of ASICs for ML tasks, the DARPA agency is launching a new program – Real Time Machine Learning (RTML). This real-time machine learning program aims to develop a compiler or software platform that can automatically design the chip architecture for a specific ML framework. The platform should automatically analyze the proposed algorithm for machine learning and the training data set for that algorithm, after which it should generate code in Verilog for creating a specialized ASIC. ML algorithm developers do not possess the knowledge of chip designers, and designers are rarely familiar with the principles of machine learning. The RTML program should facilitate the merging of the strengths of both groups into an automated platform for designing ASICs for machine learning.
During the lifecycle of the RTML program, the solutions found will need to be validated in two main application areas: operation in 5G networks and image processing. The RTML program and the developed software platforms for automated design of ML accelerators will also be utilized for developing and testing new ML algorithms and datasets. Thus, even before the design of the 'silicon', the potential of new frameworks can be assessed. The National Science Foundation (NSF), which is also addressing machine learning issues and developing ML algorithms, will partner with DARPA on the RTML program. The developed compiler will be handed over to the NSF, while DARPA expects to receive a compiler and platform for designing ML algorithms in return. In the future, hardware design and algorithm development will become a comprehensive solution, leading to the emergence of real-time self-learning machine systems.
Source: 3dnews.ru
