In the architecture of x86 platforms, two currents have emerged that complement each other. According to one version, it is necessary to move towards the integration of computing and control resources in one crystal. The second approach professes the distribution of duties: the processor is equipped with a productive bus that forms a peripheral scalable ecosystem. It forms the basis of the topology of the Intel C620 system logic for high-level platforms.
The fundamental difference from the previous Intel C610 chipset is the expansion of the communication channel between the processor and the peripherals included in the PCH chip through the use of PCIe links along with the traditional DMI bus.
Let's take a closer look at the innovations of the Intel Lewisburg South Bridge: what evolutionary and revolutionary approaches have extended its authority in communicating with processors?
Evolutionary Changes in CPU-PCH Communication
As part of the evolutionary approach, the main communication channel of the CPU with the south bridge, which is the DMI (Direct Media Interface) bus, received support for the PCIe x4 Gen3 mode with a performance of 8.0 GT/S. Previously, in the Intel C610 PCH, communication between the processor and system logic was performed in PCIe x4 Gen 2 mode at a bandwidth of 5.0 GT/S.
Comparison of functionality of system logic of Intel C610 and C620
Note that this subsystem is much more conservative than the built-in PCIe ports of the processor, usually used to connect GPUs and NVMe drives, where PCIe 3.0 has long been used and a transition to PCI Express Gen4 is planned.
Revolutionary changes in CPU-PCH communication
Revolutionary changes include the addition of new PCIe CPU-PCH communication channels, called Additional Uplinks. Physically, these are two PCI Express ports operating in PCIe x8 Gen3 and PCIe x16 Gen3 modes, both are 8.0 GT/S.
For interaction between the CPU and Intel C620 PCH, 3 buses are used: DMI and two PCI Express ports
Why did you need to revise the existing communication topology with the Intel C620? First, the PCH can integrate up to 4x 10GbE network controllers with RDMA functionality. Secondly, a new and faster generation of Intel QuickAssist Technology (QAT) coprocessors is responsible for encrypting network traffic and exchange with the storage subsystem, providing hardware support for compression and encryption. And finally, the "engine of innovation" - , which will only be available to OEMs.
Scalability and Flexibility
An important property is the ability to optionally select not only the PCH connection topology, but also the priorities of the internal resources of the microcircuit in access to high-speed communication channels with the central processor (processors). In addition, in a special EPO mode (EndPoint Only Mode), the PCH connection is carried out in the status of a regular PCI Express device containing 10 GbE and Intel QAT resources. At the same time, the classic DMI interface, as well as a number of Legacy subsystems shown in black in the diagram, are disabled.
Intel C620 PCH Internal Architecture
In theory, this allows more than one Intel C620 PCH chip to be used in a system, scaling 10 GbE and Intel QAT functionality to meet performance requirements. At the same time, Legacy functions that are needed only in a single copy can be enabled only for one of the installed PCH chips.
So, the final word in design will belong to the platform developer, acting on the basis of both technological and marketing factors in accordance with the positioning of each specific product.
Source: habr.com