In the architecture of x86 platforms, two complementary directions have emerged. According to one version, there is a need to move towards the integration of computational and control resources within a single chip. The second approach advocates for the distribution of responsibilities: the processor is equipped with a powerful bus, forming a scalable peripheral ecosystem. This serves as the foundation for Intel C620's system logic topology for high-level platforms.
The fundamental difference from the previous Intel C610 chipset is the expansion of the communication channel between the processor and the peripherals within the PCH chipset, achieved through the use of PCIe links alongside the traditional DMI bus.
Let’s take a closer look at the innovations of the Intel Lewisburg southbridge: what evolutionary and revolutionary approaches have expanded its capabilities in communication with processors?
Evolutionary changes in CPU-PCH communication
Within the evolutionary approach, the main communication channel between the CPU and the southbridge, known as the DMI (Direct Media Interface) bus, has been updated to support the PCIe x4 Gen3 mode with a performance of 8.0 GT/S. Previously, in the Intel C610 PCH, communication between the processor and system logic was conducted in PCIe x4 Gen 2 mode at a bandwidth of 5.0 GT/S.
Comparison of system logic functionality between Intel C610 and C620
It is worth noting that this subsystem is significantly more conservative than the integrated PCIe ports on the processor, which are typically used for connecting GPUs and NVMe drives, where PCIe 3.0 has long been used and a transition to PCI Express Gen4 is planned.
Revolutionary changes in CPU-PCH communication
Revolutionary changes include the addition of new PCIe communication channels between the CPU and PCH, known as Additional Uplinks. Physically, these are two PCI Express ports operating in PCIe x8 Gen3 and PCIe x16 Gen3 modes, both at 8.0 GT/S.
Three buses are used for interaction between the CPU and Intel C620 PCH: DMI and two PCI Express ports.
What necessitated the reconsideration of the existing communication topology with Intel C620? First, up to 4 network controllers with 10GbE functionality supporting RDMA can be integrated within the PCH. Secondly, the encryption of network traffic and exchanges with the storage subsystem is handled by a new and faster generation of Intel QuickAssist Technology (QAT) coprocessors, which provide hardware support for compression and encryption. Finally, the “Innovation Engine” — , which will be available only to OEM manufacturers.
Scalability and Flexibility
An important feature is the optional choice of not only the PCH connection topology but also the resource priority of the chip in accessing high-speed communication channels with the central processor(s). Additionally, in a special EPO (EndPoint Only Mode), the PCH connects as a standard PCI Express device containing 10 GbE and Intel QAT resources. At the same time, the classic DMI interface and several Legacy subsystems shown in black on the diagram are disabled.
Internal Architecture of the Intel C620 PCH Chip
Theoretically, this allows for the use of more than one Intel C620 PCH chip in the system, scaling the functionality of 10 GbE and Intel QAT according to performance requirements. Legacy functions, which are only needed in a single instance, can be enabled only on one of the installed PCH chips.
Thus, the final decision in the design will belong to the platform developer, acting based on both technological and marketing factors in accordance with the positioning of each specific product.
Source: habr.com
