Linux Foundation opened a new direction - CHIPS Alliance. As part of this project, the organization will develop a free RISC-V instruction set and technologies for creating processors based on it. Let us tell you more about what is happening in this area.
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Why CHIPS Alliance appeared
Patches protecting against Meltdown and Specter in some cases servers by 50%. At the same time, new variations of vulnerabilities associated with speculative command execution are still emerging. About one of them - Information security specialists dubbed it Spoiler. This situation affects the need to revise existing hardware solutions and approaches to their development. Specifically, Intel new architecture for their processors, not subject to Meltdown and Specter.
The Linux Foundation did not stand aside either. The organization launched its own initiative - CHIPS Alliance - whose members will develop processors based on RISC-V.
What projects are already being developed
CHIPS Alliance members include Google, Western Digital (WD) and SiFive. Each of them presented their own developments. Let's talk about some of them.
RISCV-DV
The search IT giant has transferred to open source a platform for testing processors based on RISC-V. Random decision teams that check the health of the device: test transition processes, call stack, registers, etc.
For example, the , responsible for conducting a simple test of arithmetic instructions:
class riscv_arithmetic_basic_test extends riscv_instr_base_test;
`uvm_component_utils(riscv_arithmetic_basic_test)
`uvm_component_new
virtual function void randomize_cfg();
cfg.instr_cnt = 10000;
cfg.num_of_sub_program = 0;
cfg.no_fence = 1;
cfg.no_data_page = 1'b1;
cfg.no_branch_jump = 1'b1;
`DV_CHECK_RANDOMIZE_WITH_FATAL(cfg,
init_privileged_mode == MACHINE_MODE;
max_nested_loop == 0;)
`uvm_info(`gfn, $sformatf("riscv_instr_gen_config is randomized:n%0s",
cfg.sprint()), UVM_LOW)
endfunction
endclass
On developers, the platform differs from analogues in that it allows you to sequentially check all the components of the chip, including the memory unit.
OmniXtend Protocol
This is a network protocol from WD that provides cache coherence when transferring data over Ethernet. allows you to exchange messages directly with the processor cache and is used to connect various accelerators: GPU or FPGA. It is also suitable for building systems based on multiple RISC-V chips.
Protocol already supported oriented to data processing in data centers. SweRV is a 32-bit dual-pipeline superscalar processor based on a 28nm process technology. Each pipeline has nine levels, which makes it possible to load and execute several commands at the same time. The device operates at a frequency of 1,8 GHz.
Rocket Chip Generator
A solution from SiFive, which was founded by the developers of RISC-V technology. is a RISC-V processor core generator in the Chisel language. He a set of parameterized libraries that are used to create .
Concerning , then it is a hardware description language based on Scala. It generates low-level Verilog code that for processing on ASIC and FPGA. Thus, it allows you to use the principles of OOP when developing .
Alliance prospects
Experts say that the Linux Foundation initiative will make the processor market more democratic and open to new players. At IDC that the growing popularity of such projects will have a positive impact on the development of machine learning technologies and AI systems in general.
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The development of open source processors will also reduce the cost of custom chip design. However, this will only happen if the Linux Foundation can attract enough developers.
Similar projects
Other organizations are involved in the development of projects related to open hardware. An example is the CXL consortium, which introduced the Compute Express Link standard in mid-March. The technology is similar to OmniXtend and also connects CPU, GPU, FPGA. For data exchange, the standard uses the PCIe 5.0 bus.
Another project involved in the development of processor technologies is MIPS Open, which appeared in December 2018. The initiative was created by startup Wave Computing. Developers plan for the IT community access to the latest 32-bit and 64-bit MIPS instruction sets. Project start in the coming months.
In general, the open source approach is becoming generally accepted not only for software, but also for hardware. Such projects are supported by large companies. Therefore, we can expect that in the near future more devices based on open hardware standards will appear on the market.
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Source: habr.com