ARM has introduced its latest processor design β the Cortex-A77. Like last year's Cortex-A76, this core is aimed at high-end tasks in smartphones and various devices. The developer focuses on increasing the number of instructions executed per cycle (IPC). Clock speeds and power consumption remain roughly on par with Cortex-A76.
Currently, ARM aims to rapidly enhance the performance of its cores. According to its plans, starting from the Cortex-A73 in 2016 up to the Hercules design in 2020, the company intends to increase CPU power by 2.5 times. The transitions from 16 nm to 10 nm and then to 7 nm have already allowed for higher clock speeds, and combined with the Cortex-A75 architecture and then the Cortex-A76, ARM estimates a current 1.8-fold performance increase. Now, the Cortex-A77 core will enable a further 20% performance boost at the same clock frequency due to the increase in IPC. This means that a 2.5-fold increase in 2020 is quite achievable.
Despite the 20% increase in IPC, ARM estimates that the power consumption of the A77 has not increased. The trade-off here is that the die area of the A77 is about 17% larger than that of the A76 at the same technology nodes. As a result, the cost of an individual core will rise slightly. When comparing ARM's achievement with industry leaders, it's worth noting that AMD achieved a 15% IPC increase in Zen 2 compared to Zen+, while Intel's core IPC values have remained roughly the same for many years.
The out-of-order execution window size has been increased by 25%, to 160 entries, allowing the core to enhance parallelism in calculations. Even in the Cortex-A76, there was a large branch target buffer, and in the Cortex-A77, it has been increased by an additional 33%, to 8 KB, enabling the branch prediction unit to effectively handle the rise in the number of parallel instructions.
An even more interesting innovation is the completely new 1.5-Kbyte cache that stores macro-operations (MOP) returned from the decoding module. The ARM processor architecture decodes instructions from the user application into smaller macro-operations and then breaks them down into micro-operations that are passed on to the execution core. The MOP cache helps reduce the impact of missed branches and resets, as macro-operations are now stored in a separate block and do not require re-decoding, thus increasing the overall throughput of the core. In certain workloads, the new block is an extremely useful addition to the standard instruction cache.
A fourth ALU block and a second branching block have been added to the execution core. The fourth ALU increases the overall throughput of the processor by 1.5 times due to the capability of executing single-cycle instructions (such as ADD and SUB) and two-cycle integer operations like multiplication. The other two ALUs can only handle basic single-cycle instructions, while the last block is tasked with more complex mathematical operations such as division, accumulation multiplication, and so on. The second branching block within the execution core doubles the number of simultaneous branch transitions that the core can handle, which is beneficial in cases where two of the six dispatched commands involve branch transitions. Internal testing at ARM has shown a performance gain from utilizing this second branch transition block.
Among other changes in the core are the addition of a second AES encryption pipeline, increased memory bandwidth, an enhanced next-generation data prefetching mechanism that improves energy efficiency while simultaneously increasing the bandwidth of the DRAM system, cache operation optimizations, and more.
The most significant gains are observed in the Cortex-A77 for integer operations and floating-point calculations. This is confirmed by ARM's internal testing in SPEC, which showed a performance increase of 20% and 35% in integer operations and floating-point calculations, respectively. Memory bandwidth improvements are somewhere in the range of 15-20%. Overall, optimizations and changes in the A77 provide an average 20% performance boost compared to the previous generation. With newer technology standards like 7nm ULV, we can gain additional advantages in end chips.
ARM developed the Cortex-A77 to work in a 4+4 big.LITTLE configuration (4 powerful cores and 4 simple power-efficient ones). However, considering the increased area of the new architecture, many manufacturers may propose combinations of 1+3+4 or 2+2+4 for cost-saving purposes, which are already actively practiced, where only one or two cores will be full-fledged uncensored A77.
Source: 3dnews.ru
