The release of the Vortex 2.2 project has been published, which develops an open GPGPU based on the RISC-V instruction set architecture, aimed at performing parallel computations using the OpenCL API and the SIMT (Single Instruction, Multiple Threads) execution model. The project can also be used for research in the field of 3D graphics and for developing new GPU architectures. Schematics, hardware block descriptions in Verilog, a simulator, drivers, and accompanying project documentation are distributed under the Apache 2.0 license.
The foundation of GPGPU consists of a typical RISC-V ISA, enhanced with additional instructions necessary to support GPU functions and thread management. Changes to the RISC-V architecture are minimized, and existing vector instructions are utilized wherever possible. Among the additional instructions are: 'tex' for accelerating texture processing, vx_rast for rasterization control, vx_rop for fragment processing, depth, and transparency, vx_imadd for performing 'multiply and add' operations, and vx_wspawn, vx_tmc, and vx_bar for activating instruction and thread fronts (wavefront, a set of threads executed in parallel by the SIMD Engine), vx_split and vx_join.
The developed GPGPU supports 32- and 64-bit RISC-V RV32IMF and RV64IMAFD instruction set architectures and may include optional shared memory, L1, L2, and L3 caches, as well as a customizable number of cores, warps, and threads. Each core is designed to allow a configurable number of ALU, FPU, LSU, and SFU. Prototypes can utilize Altera Arria 10 FPGA, Altera Stratix 10, Xilinx Alveo U50, U250, U280, and Xilinx Versal VCK5000. For simulating chip operation, Verilator (Verilog simulator), RTLSIM (RTL simulation), and SimX (software simulation) may be used.
The development of applications is supported by a toolkit that includes Vortex-adapted versions of PoCL (OpenCL compiler and runtime), LLVM/Clang, GCC, and Binutils. The project supports the OpenCL 1.2 specification and has implemented support for the SPIR-V intermediate representation of shaders via translation to OpenCL. For graphics on Vortex technologies, an open GPU Skybox is being developed, supporting the Vulkan graphics API. The Skybox prototype, built on the Altera Stratix 10 FPGA and featuring 32 cores (512 threads), achieved a fill rate of 3.7 gigapixels per second (29.4 gigatransactions per second) at a clock speed of 230 MHz.
Among the changes in version Vortex 2.2:
- The API vx_spawn_taskgroups has been added for launching cores that support segmented execution of 3D tasks.
- Support for ZICOND, an extension of the RISC-V instruction set architecture that allows conditional execution of operations without branching, has been added.
- The OpenCL compiler has been transitioned to thread-level scheduling (where each thread executes its task independently of other threads), rather than task groups (warp-level) as before.
- Support for JIT compilation and 64-bit cores has been added to OpenCL.
- Support for dynamic loading of the Vortex runtime has been implemented.
- New documentation for configuring Xilinx FPGA has been proposed.
- Logic synthesis testing using Yosys tooling has been included.
- Cache support has been provided for hierarchical flush operations and in write-back mode.
- Optimization of verification speed for scoreboard and operand processing at the register transfer level (RTL) has been conducted.
- Support for the Ramulator 2.0 DRAM memory simulator has been added.
- The transition to new versions of Verilator 5.0 (SystemVerilog simulator) and LLVM 18.0 has been completed, along with an update to the toolset based on CentOS 7.9.
- GitHub CI has been adopted instead of the Travis CI continuous integration system.
Source: opennet.ru
