On June 2, Eric Biggers (an engineer from Google) introduced new AES-XTS implementations for significantly higher performance on Intel/AMD processors using new AES-NI + AVX, VAES + AVX2, VAES + AVX10/256, and VAES + AVX10/512 code sets.
The AES-NI GCM code replaces the previous version written by Intel and addresses existing issues:
"This update set adds AES-GCM (Galois/Counter mode) implementation in VAES and AVX512/AVX10, enhancing AES-GCM performance by up to 162%. Additionally, it replaces the old Intel AES-NI GCM code with new code that is slightly faster and fixes several issues, including the large binary file size exceeding 250 KB. For more details, see the patches."
The final state of the x86_64 AES-GCM assembly code results in two assembly files: one generates AES-NI code with or without AVX, while the other generates VAES code with AVX512/AVX10 using 256-bit or 512-bit vectors. It does not support single VAES (without AVX512/AVX10). This is somewhat different from what I did with AES-XTS, where one file generates AVX and AVX512/AVX10 code, including code that uses only VAES (without AVX512/AVX10), and the other generates only non-AVX code. However, at this moment, this seems to be the right choice for each specific algorithm, considering that the limitation to 16 SIMD registers and 128-bit vectors has led to significantly differing constructive solutions in AES-GCM but not so much for AES-XTS. Processors provided only with VAES also appear to be a temporary phenomenon, so we might not want to push too hard for supporting this combination."
Source: linux.org.ru
