The Vortex 3.0 project, which develops an open-source GPGPU based on the RISC-V instruction set architecture and is designed for parallel computing using the OpenCL API and the SIMT (Single Instruction, Multiple Threads) execution model, is now available. The project can also be used for 3D graphics research and the development of new GPU architectures. The schematics, hardware block descriptions in Verilog, simulator, drivers, and accompanying design documentation are distributed under the Apache 2.0 license.
GPGPU is based on the standard RISC-V ISA, extended with additional instructions to support GPU features and thread management. Changes to the RISC-V instruction set architecture are kept to a minimum, and existing vector instructions are used whenever possible. Additional instructions include: "tex" for accelerating texture processing; vx_rast for rasterization control; vx_rop for fragment, depth, and transparency processing; vx_imadd for multiply-and-add operations; vx_wspawn, vx_split, vx_join, vx_tmc, and vx_bar for activating groups of threads (wavefronts) executed in parallel by the SIMD Engine.
The GPGPU being developed supports 32- and 64-bit RISC-V RV32IMF and RV64IMAFD instruction set architectures and can include optional shared memory, L1, L2, and L3 caches, and a configurable number of cores, warps, and threads. Each core can also include a configurable number of ALUs, FPUs, LSUs, and SFUs. Xilinx and Altera FPGAs can be used for prototyping, and Verilator (Verilog simulator), RTLSIM (RTL simulation), and SimX (software simulation) can be used for chip simulation.
For application development, a toolkit is offered, including Vortex-adapted versions of PoCL (OpenCL compiler and runtime), LLVM/Clang, GCC, and Binutils. The project supports the OpenCL 1.2 specification and implements support for the SPIR-V intermediate representation of shaders via translation to OpenCL.
Changes in Vortex 3.0 include:
- A hardware graphics stack has been added, including blocks for rasterization, texture mapping, and output merging (OM). A Vulkan driver, vortexpipe, has been developed for Mesa based on the implemented graphics stack and the lavapipe software rasterizer.
- The capabilities of the Tensor Core, designed to accelerate the execution of machine learning models, have been expanded, implementing support for structured sparsity for compressing weight matrices.
- The WGMMA (warpgroup-level matrix multiplication) operation has been implemented for matrix multiplication in asynchronous mode.
- Added DXA (Data Transfer Acceleration) engine to speed up data transfer from global to local memory.
- A new architecture has been implemented based on a command processor (CP) and a hardware scheduler of computing cores (KMU - Kernel Management Unit), which allows the dispatching of computing threads to the chip side.
- A new runtime library is proposed that operates in non-blocking mode and provides abstractions that translate into asynchronously executed hardware commands. Queues, events, modules, and synchronization based on asynchronous barriers with arrive/wait/event semantics are supported.
- Added support for RISC-V Shortened Instructions (RVC).
- Hardware support for atomic operations (Hardware Atomics) has been implemented.
- The FPU has been completely redesigned and new multiplier (Wallace-tree, Folded-radix) and adder (Kogge-Stone) blocks have been introduced.
- Added a virtual memory stack based on the memory management unit (MMU) with support for the 32-bit SV32 virtual addressing architecture.
- Support for the RISC-V Zicond extension with implementation of conditional operations.
- Integrated clock gating.
- Support for the HIP (Heterogeneous Interface for Portability) language has been implemented through the chipStar framework, which translates HIP into SPIR-V.
- Full integration with the GEM5 simulator has been provided, and support for the SimX simulator on the TLM (Transaction-Level Modeling) architecture has been added.
- Added support for Synopsys and Yosys toolkits for logic synthesis for chip manufacturing, as well as support for using the ASAP7 (7nm), SAED14 (14nm), and NanGate (15nm) standard element libraries.
- The reference toolchain has been updated to LLVM 20 and POCL 7.0.
Source: opennet.ru
