The release of the Vortex 3.0 project is now available, which develops an open GPGPU based on the RISC-V instruction set architecture designed for parallel computing using the OpenCL API and the SIMT (Single Instruction, Multiple Threads) execution model. The project can also be used for research in 3D graphics and the development of new GPU architectures. Schematics, hardware block descriptions in Verilog, simulators, drivers, and accompanying project documentation are distributed under the Apache 2.0 license.
The GPGPU is based on a standard RISC-V ISA, extended with additional instructions to support GPU functions and thread management. Changes to the RISC-V instruction set architecture are minimized and, where possible, use existing vector instructions. Among the additional instructions are: 'tex' to accelerate texture processing; vx_rast for managing rasterization, vx_rop for fragment processing, depth, and transparency; vx_imadd for performing the 'multiply and add' operation; vx_wspawn, vx_split, vx_join, vx_tmc, and vx_bar for activating groups of threads (wavefronts) executed in parallel by the SIMD Engine.
The developed GPGPU supports 32-bit and 64-bit RISC-V instruction set architectures RV32IMF and RV64IMAFD, and can include optional shared memory, L1, L2, and L3 level caches, as well as a customizable number of cores, warps, and threads. Each core also allows for the enabling of a customizable number of ALU, FPU, LSU, and SFU. Prototyping can use Xilinx and Altera FPGAs, while chip operation simulation can utilize Verilator (Verilog simulator), RTLSIM (RTL simulation), and SimX (software simulation).
For application development, a toolkit is provided, including Vortex-adapted versions of PoCL (OpenCL compiler and runtime), LLVM/Clang, GCC, and Binutils. The project supports the OpenCL 1.2 specification and implements support for the intermediate shader representation SPIR-V via translation to OpenCL.
Among the changes in Vortex 3.0:
- A hardware graphics stack has been added, including blocks for rasterization, texture overlay, and output merging (OM - Output Merger). For Mesa, based on the implemented graphics stack and the software rasterizer lavapipe, a Vulkan driver vortexpipe has been prepared.
- Expanded capabilities of the tensor core designed to accelerate machine learning model execution, with support for structured sparsity implemented for compressing weight matrices.
- The WGMMA (warpgroup-level matrix multiplication) operation has been implemented for asynchronous matrix multiplication.
- A DXA (Data Transfer Acceleration) engine has been added to speed up data transfer from global to local memory.
- A new architecture based on the Command Processor (CP) and a hardware scheduler of computational cores (KMU – Kernel Management Unit) has been developed, allowing for the offloading of computational thread dispatching operations to the chip side.
- A new runtime library operating in a non-blocking mode has been proposed, providing abstractions translated into hardware asynchronously executed commands. Support is available for queues, events, modules, and synchronization based on asynchronous barriers with arrive/wait/event semantics.
- Support for RISC-V compressed instructions (RVC) has been added.
- Hardware support for atomic operations (Hardware Atomics) has been implemented.
- The FPU has been completely redesigned and new multiplier blocks (Wallace-tree, Folded-radix) and adders (Kogge-Stone) have been proposed.
- A virtual memory stack based on the memory management unit (MMU) has been added, supporting 32-bit architecture of virtual addressing SV32.
- Support for the RISC-V extension Zicond with the implementation of conditional operations has been added.
- Clock gating for frequency management has been integrated.
- Support for the HIP (Heterogeneous Interface for Portability) language through the chipStar framework, which translates HIP into SPIR-V, has been implemented.
- Full integration with the GEM5 simulator has been ensured and support for the SimX simulator on the TLM (Transaction-Level Modeling) architecture has been added.
- Support for Synopsys and Yosys toolchains for logic synthesis for chip production has been added, along with support for using standard cell libraries ASAP7 (7nm), SAED14 (14nm), and NanGate (15nm).
- The benchmark toolset has been updated to LLVM 20 and POCL 7.0.
Source: opennet.ru
