The release of the CoreBoot project on 25.09, which develops a free alternative to proprietary firmware and BIOS, has been published. The project's code is distributed under the GPLv2 license. The new version includes 684 changes prepared with the participation of 110 developers.
Key Changes:
- Support for motherboards has been implemented:
- ASROCK SPC741D8-2L2T/BCM.
- GIGABYTE GA_H81M_D2W.
- HP 260 G1 DM, HP Compaq Pro 6300 SFF/MT, HP ProDesk 600 G1 SFF.
- Intel Ptlrvp4es
- Lenovo ThinkPad T480/T480s.
- 11 boards used in various devices with Chrome OS or on servers Google.
- The loading of SPI Flash and payload components has been significantly accelerated. When building in CONFIG_SSE mode, the unpacking code based on LZMA algorithm utilizes SSE prefetch instructions, allowing for preloading data into the CPU cache without interrupting the unpacking operation. Testing the SPI interface with a bandwidth of 100Mbit/s on mobile Intel Sandy Bridge CPUs achieved a reduction in boot time by 46 ms and a 30% speedup in the unpacking of payload components.
For Intel Panther Lake platforms, support for asynchronous file loading has been implemented, utilizing SPI DMA for preloading the fsps.bin file concurrently with CPU executing other tasks. On Fatcat devices, this optimization improved load times by 17-18 ms. The efficiency of DMA operations has been enhanced. A new synchronization function cbfs_preload_wait_for_all() has been added, allowing for safe completion of asynchronous operations before storage backends are deactivated. In the Fast SPI DMA subsystem, a token-based data transmission queue has been implemented, minimizing delays between consecutive DMA operations and providing more predictable load performance.
- The capability for boot mode detection has been implemented, allowing platforms to pass critical information about the boot state to payload components. Support is provided for detecting normal boot mode, low battery mode, and battery charging mode through a standardized boot_mode_t interface.
- The management of MTRR (Memory Type Range Registers) for video memory has been revised, which reduced the initialization time of FSP-S (Firmware Support Package — Silicon) by moving the configuration of MTRR WC (Write-Combine) for video memory from the logo rendering functions to the chip initialization stage. As a result, the initialization time of the graphics subsystem decreased from 123 to 115 ms. The redesign also simplified code maintenance by separating MTRR management and logo rendering functions.
- The amdfwtool utility, designed for working with AMD firmware, has improved address mode handling and expanded EFW structure parsing capabilities on the Turin platform.
- The smmstoretool utility now supports variable block sizes and aliasing of GUID partition tables in Secure Boot mode to enhance UEFI variable management.
- TPM support has been extended for various platforms with CRB TPM and improved integration of fTPM for AMD platforms.
- Logo rendering has been improved.
- Compatibility with the Bochs display driver has been enhanced.
- The cbfstool utility's stability has been increased when sorting the FIT table and in case of failures during compression operations.
- Changes have been made for Intel, AMD, MediaTek, and Qualcomm platforms to improve power management, memory initialization, and support for hardware interfaces.
- Updated versions of binutils 2.44, ACPICA 20250404, MPFR 4.2.2, SeaBIOS 1.17.0, U-Boot 2025.07.
Source: opennet.ru
