The release of CoreBoot 4.14 has been announced, within which a free alternative to proprietary firmware and BIOS is being developed. A total of 215 developers participated in creating the new version, preparing 3660 changes.
Key innovations:
- Initial support for AMD Cezanne APU has been implemented, and a general code reorganization has been conducted to support AMD's SoCs. The pattern code for AMD SoCs has been unified, allowing components already available for SoC Picasso to be utilized in the code for AMD Cezanne.
- Support for second and third generation Intel Xeon Scalable (Xeon-SP) server processors — SkyLake-SP (SKX-SP) and CooperLake-SP (CPX-SP) — has been stabilized and is recognized as ready for production deployment. The SKX-SP code has been used to support OCP TiogaPass motherboards, while CPX-SP has been used for OCP DeltaLake. The codebase for supporting different generations of Xeon-SP has been optimized and unified.
- Support has been added for 42 motherboards, 25 of which are used on devices with Chrome OS or on servers Google. Among the unrelated to Google boards:
- AMD Bilby and AMD Majolica;
- GIGABYTE GA-D510UD;
- HP 280 G2;
- Intel Alderlake-M RVP, Intel Alderlake-M RVP, Intel Elkhartlake LPDDR4x CRB, and Intel shadowmountain;
- Kontron COMe-mAL10;
- MSI H81M-P33 (MS-7817 v1.2);
- Pine64 ROCKPro64;
- Purism Librem 14;
- System76 darp5, galp3-c, gaze15, oryp5 and oryp6.
- Support for Intel Cannonlake U LPDDR4 RVP motherboards, Intel Cannonlake U LPDDR4 RVP, and Google Boldar has been discontinued.
- A centralized ACPI GNVS framework has been introduced, which is used instead of the SMI handlers APM_CNT_GNVS_UPDATE and is now utilized for initializing typical elements of ACPI GNVS tables.
- The file system format of CBFS, used for placing Coreboot components on Flash, has been changed. The changes reflect the preparation for implementing the capability to sign individual files with digital signatures.
Source: opennet.ru
