The release of CoreBoot 4.22 is available, which develops a free alternative to proprietary firmware and BIOS. The project's code is distributed under the GPLv2 license. A total of 135 developers participated in creating the new version, preparing 977 changes. It is noted that starting from the next release, the project will switch to a new version naming scheme tied to the date (year.month.update); for example, in February 2024, instead of version 4.23, a release will be formed as 24.02.00.
Key Changes:
- An initial implementation of the AMD openSIL platform (Open-Source Silicon Initialization Library) has been added, which develops components to simplify firmware creation.
- Support for 17 motherboards has been added. 11 of the added boards are used in devices running Chrome OS or on servers Google. Boards unrelated to Google include:
- AMD Onyx
- Intel Meteorlake-P RVP
- Purism Librem 11
- Purism Librem L1UM v2
- Siemens FA EHL
- Supermicro X11SSW-F
- Support for AMD Genoa SoC has been added.
- Support for the '.data' section has been implemented on the x86 architecture in the pre-memory initialization stages, allowing the use of global variable definitions in C code. At the boot block stage, data is attached immediately after the code and is then placed in the cache using the Cache-As-RAM (VMA) concept.
- For x86 systems at the ramstage and pre-memory initialization stages, support for the CBFS filesystem cache has been implemented, which is used for placing Coreboot components in Flash. The CBFS cache allows uncompressing CBFS files by using the cbfs_map() function without reserving a separate memory area for the file. The parameters PRERAM_CBFS_CACHE_SIZE and RAMSTAGE_CBFS_CACHE_SIZE are suggested for configuring cache size.
- The ability to embed romstage in the boot block has been added. Delivering romstage as part of the boot block allows the code size to be reduced by 10-20 thousand lines. Situations where a separate delivery of romstage may be required include configurations with vboot or fallback mode, as well as devices with a limited boot block size (Intel APL 32K) or excessively slow boot media (some ARM SoCs).
- An API has been added in gfx to detect the presence of an external display on devices with Intel chips.
- The ability to add a checksum for VBIOS when filling the VFCT table has been implemented in pci_rom. Such checksums are checked by some AMD drivers for Windows.
- Changes have been made to enable Windows to run on certain Chromebook devices with Coreboot.
- Implemented ACPI table generation for devices based on the ARM64 architecture.
- Improved compatibility with ACPI specifications.
- MRC (Memory Reference Code) settings for SNB+MRC boards have been moved to the DeviceTree structure.
- Updated payload components based on U-Boot and edk2.
- The toolset has been updated: GMP 6.3.0, binutils 2.41, and MPFR 4.2.1.
- The main branch in the Git repository has been renamed from 'master' to 'main'.
Source: opennet.ru
