ARM has unveiled its latest processor design, the Cortex-A77. Like last year's Cortex-A76, this core is designed for high-end tasks in smartphones and a wide variety of devices. In it, the developer aims to increase the number of commands executed per cycle (IPC). Clock speeds and power consumption remained approximately at the level of Cortex-A76.
Currently, ARM aims to quickly increase the performance of its cores. According to its plans, starting with the 73 Cortex-A2016 and up to the 2020 Hercules design, the company intends to increase the CPU power by 2,5 times. Already transitions from 16 nm to 10 nm and then to 7 nm made it possible to increase the clock frequency, and in combination with the Cortex-A75 and then Cortex-A76 architecture, according to ARM estimates, a 1,8-fold increase in performance has been achieved to date. Now the Cortex-A77 core will allow, due to the growth of IPC, to increase performance by another 20% at the same clock frequency. That is, a 2,5-fold increase in 2020 is becoming quite real.
Despite a 20% increase in IPC, ARM estimates that the A77's power consumption has not increased. The trade-off in this case is that the A77 die area is about 17% larger than A76 at the same process rates. As a result, the cost of a single core will increase slightly. If we compare the achievement of ARM with the industry leaders, then it is worth saying that AMD in Zen 2 achieved a 15% increase in IPC compared to Zen +, and the IPC value of Intel cores has remained at about the same level for many years.
The execution window with a change in the sequence of commands (out-of-order window size) is increased by 25%, up to 160 units, which allows the kernel to increase the parallelism of calculations. Even the Cortex-A76 had a large Branch Target Buffer, and in the Cortex-A77 it was increased by another 33%, to 8 KB, which allows the branch prediction block to effectively cope with the increase in the number of parallel instructions.
Even more interesting is a completely new 1,5 KB cache that stores macro operations (MOPs) returned from the decode module. The ARM processor architecture decodes instructions from the user application into smaller macro-ops, and then breaks them down into micro-ops that are passed to the execution core. The MOP cache is used to reduce the impact of skipped branches and flushes, since macro operations are now stored in a separate block and do not require re-decoding - thereby increasing the overall throughput of the core. In some workloads, the new block is a very useful addition to the standard instruction cache.
The fourth ALU block and the second branching block have been added to the execution core. The fourth ALU increases the overall throughput of the processor by 1,5 times due to the ability to execute single-cycle instructions (such as ADD and SUB) and two-cycle integer operations such as multiplication. The other two ALUs can only handle basic single-cycle instructions, while the last block is loaded with more complex math operations such as division, multiply-accumulate, etc. The second branch unit inside the execution core doubles the number of simultaneous branch transitions the core can handle. work, which is useful in cases where two of the six commands sent are branch transitions. Internal testing at ARM has shown a performance benefit from using this second jump block.
Other core changes include the addition of a second AES encryption pipeline, increased memory bandwidth, improved next-generation data prefetching to improve power efficiency while increasing DRAM system throughput, cache optimizations, and more.
The biggest increase is observed in Cortex-A77 in integer operations and floating point calculations. This is backed up by ARM's internal tests at SPEC, which showed performance improvements of 20% and 35% in integer and floating point operations, respectively. Memory bandwidth improvements are somewhere in the 15-20% range. Overall, the optimizations and changes to the A77 average out a 20 percent performance boost over the previous generation. With newer technology standards like 7nm ULV, we can get additional benefits in the final chips.
ARM designed the Cortex-A77 to work in a 4+4 big.LITTLE bundle (4 powerful cores and 4 simple energy efficient ones). But, given the increased area of the new architecture, many manufacturers, in order to save money, can introduce bundles of 1 + 3 + 4 or 2 + 2 + 4, which are already actively practiced, where only one or two cores will be full-fledged uncut A77.
Source: 3dnews.ru
