ASICs for machine learning should be designed automatically

It is unlikely that anyone will argue with the fact that the design of custom LSI (ASIC) is far from a simple and fast process. But I want and need it to be faster: today I issued an algorithm, and a week later I took the finished digital project. The fact is that super-specialized LSI is almost a piece product. These are rarely needed in millions of batches, the development of which can be spent any amount of money and human resources, if it needs to be done in the shortest possible time. Specialized, and therefore the most effective ASICs for solving their problems, should be cheaper in development, which is becoming mega-relevant at the present stage of machine learning development. On this front, the baggage accumulated by the computer market and, especially, GPU breakthroughs in the field of machine learning (ML) can no longer be dispensed with.

ASICs for machine learning should be designed automatically

To accelerate ASIC design for ML tasks, DARPA is establishing a new program called Real Time Machine Learning (RTML). The real-time machine learning program involves the development of a compiler or software platform that could automatically design a chip architecture for a specific ML framework. The platform should automatically analyze the proposed algorithm for machine learning and the data set for training this algorithm, after which it will have to issue code in the Verilog language to create a specialized ASIC. ML algorithm developers do not have the knowledge of chip designers, and designers are rarely familiar with the principles of machine learning. The RTML program should help bring the benefits of both together in an automated ASIC development platform for machine learning.

During the life cycle of the RTML program, the solutions found will have to be tested in two main areas of application: work in 5G networks and image processing. Also, the RTML program and the created software platforms for the automatic design of ML accelerators will be used to develop and test new ML algorithms and data sets. Thus, even before the design of silicon, it will be possible to assess the prospects for new frameworks. DARPA's partner in the RTML program will be the National Science Foundation (NSF), which also deals with machine learning and the development of ML algorithms. The developed compiler will be transferred to NSF, and DARPA expects to receive a compiler and a platform for designing ML algorithms back. In the future, hardware design and creation of algorithms will be a complex solution, which will lead to the emergence of self-learning machine systems in real time.




Source: 3dnews.ru

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