A team of researchers from the Vrije Universiteit Amsterdam has identified a new (CVE-2020-0543) in the microarchitectural structures of Intel processors, notable in that it allows you to restore the results of the execution of some instructions executed on another CPU core. This is the first vulnerability in the speculative instruction execution mechanism that allows data leakage between individual CPU cores (previously leaks were limited to different threads of the same core). The researchers named the problem CROSSTalk, but The vulnerability is referred to as SRBDS (Special Register Buffer Data Sampling).
The vulnerability relates to a year ago to the class of MDS (Microarchitectural Data Sampling) problems and is based on the application of side-channel analysis methods to data in microarchitectural structures. CROSSTalk is close to vulnerability , but differs in the source of the leak.
The new vulnerability manipulates the leak of a previously undocumented intermediate buffer that is shared by all CPU cores.
is that some microprocessor instructions, including RDRAND, RDSEED and SGX EGETKEY, are implemented using the internal microarchitectural SRR (Special Register Reads) operation. On affected processors, the data returned for SRR is deposited in an intermediate buffer common to all CPU cores, after which it is transferred to a fill buffer associated with the specific physical CPU core on which the read operation was initiated. Next, the value from the fill buffer is copied into registers visible to applications.
The size of the intermediate shared buffer corresponds to the cache line, which is usually larger than the size of the data being read, and different reads affect different offsets in the buffer. Since the shared buffer is copied entirely to the fill buffer, not only the portion needed for the current operation is moved, but also the data remaining from other operations, including those performed on other CPU cores.
If the attack is successful, a local user authenticated in the system can determine the result of executing the RDRAND, RDSEED and EGETKEY instructions in a foreign process or inside an Intel SGX enclave, regardless of the CPU core on which the code is executed.
Researchers who identified the problem A prototype exploit demonstrating the ability to leak information about random values ββobtained through the RDRAND and RDSEED instructions to recover an ECDSA private key processed in the Intel SGX enclave after performing only one digital signature operation on the system.
problem a wide range of desktop, mobile and server Intel processors, including Core i3, i5, i7, i9, m3, Celeron (J, G and N series), Atom (C, E and X series), Xeon (E3, E5, E7 families , W and D), Xeon Scalable, etc. It is noteworthy that Intel was notified of the vulnerability in September 2018, and in July 2019 an exploit prototype was provided demonstrating data leakage between CPU cores, but the development of a fix was delayed due to the complexity of its implementation. Today's proposed microcode update addresses the issue by changing the behavior of the RDRAND, RDSEED, and EGETKEY instructions to overwrite data in the shared buffer to prevent residual information from settling there. In addition, buffer access is paused until the contents are read and rewritten.
A side effect of this type of protection is increased latency when executing RDRAND, RDSEED, and EGETKEY, and reduced throughput when attempting to execute these instructions simultaneously on different logical processors. Executing RDRAND, RDSEED, and EGETKEY also suspends memory access from other logical processors. These features may negatively affect the performance of some server applications, so the firmware provides a mechanism (RNGDS_MITG_DIS) to disable protection for RDRAND and RDSEED instructions executed outside the Intel SGX enclave.
Source: opennet.ru