Long , that with the 3nm process technology, transistors will move from vertical "finned" FinFET channels to horizontal nanopage channels completely surrounded by gates or GAA (gate-all-around). Today, the French institute CEA-Leti showed how FinFET manufacturing processes can be used to produce multilevel GAA transistors. And maintaining the continuity of technological processes is a reliable basis for rapid transformation.
For the VLSI Technology & Circuits 2020 Symposium CEA-Leti specialists about the production of a seven-level GAA transistor (special thanks to the coronavirus pandemic, thanks to which speech documents finally began to appear quickly, and not months later after conferences). French researchers have proven that they can produce GAA transistors with channels in the form of a whole “stack” of nanopages using the widely used technology of the so-called RMG process (replacement metal gate or, in Russian, replacing (temporary) metal gate). At one time, the RMG process technology was adapted for the production of FinFET transistors and, as we see, can be extended to the production of GAA transistors with a multilevel arrangement of nanopage channels.
Samsung, as far as we know, with the start of production of 3-nm chips plans to produce two-level GAA transistors with two flat channels (nanopages) located one above the other, surrounded by a gate on all sides. CEA-Leti specialists have shown that it is possible to produce transistors with seven nanopage channels and at the same time set the channels to the desired width. For example, the experimental seven-channel GAA transistor was released in widths from 15nm to 85nm. It is clear that this allows you to set precise characteristics for transistors and guarantee their repeatability (reduce the spread of parameters).
According to the French, the more channel levels in a GAA transistor, the greater the effective width of the total channel and, therefore, the better controllability of the transistor. Also, in a multilayer structure, there are less leakage currents. For example, a seven-level GAA transistor has three times less leakage current than a two-level one (conditionally, like the Samsung GAA). Well, the industry has finally found its way up, moving away from the horizontal placement of elements on a chip to a vertical one. It seems that chips still do not have to increase the area of \uXNUMXb\uXNUMXbcrystals in order to become even faster, more powerful and more energy efficient.
Source: 3dnews.ru