Google has partnered with manufacturing companies SkyWater Technology and Efabless to launch an initiative to allow open source hardware developers to build the chips they develop for free. The initiative is aimed at stimulating the development of open hardware, reducing the costs of developing open projects and simplifying interaction with manufacturing plants. Thanks to the initiative, anyone can start developing their own specialized chips without fear of high costs for the production of initial prototypes. All production, packaging and shipping costs are covered by Google.
Applications for inclusion in the free production program can be submitted every two months. The nearest slot will be closed on June 8, and the chips that managed to get into it will be ready on August 30 and sent to the authors on October 18. Of the submitted applications, 40 projects are selected (if there are less than 40 submitted applications, then all those that have passed the correctness check will be put into production). According to the production results, the developer will receive 50 chips and 5 boards with installed chips.
Applications are accepted only from projects that are fully distributed under open licenses, not burdened by non-disclosure agreements (NDA) and not restricting the scope of their products. Data for production must be transferred in the GDSII format, pass the provided test set and be reproduced from the original project files (i.e. declare an open project, but it will not work to transfer a proprietary layout for production).
To simplify the development of open chips, the following open tools are offered:
- SkyWater PDK (Process Design Kit), a toolkit that describes the 130nm (SKY130) process technology used at the SkyWater factory and allows you to prepare the design files necessary for the production of microcircuits.
- OpenLane is a set of components for automated conversion of ASIC RTL circuitry to the GDSII format used in chip factories.
- XLS (Accelerated HW Synthesis) is a toolkit for synthesizing project files with hardware stuffing of chips that correspond to the provided high-level description of the required functionality, designed in the style of software development.
- A set of rules for the Bazel assembly system with support for open tools (Yosys, Verilator, OpenROAD) for working with hardware description languages ββ(Verilog, VHDL, Chisel, nMigen).
- OpenROAD is a framework for automating the process of developing open circuits.
- Verible is a set of tools for Verilog development, including a parser, style formatting system, and linter.
Source: opennet.ru