The Libre-SOC project, which develops an open chip with a CDC 6600-style hybrid architecture implementation in which the CPU, VPU, and GPU instructions are not separated and proposed in a single ISA to reduce the size and complexity of the chip, has reached the stage of transfer to production of the first test sample. The project originally developed under the name Libre RISC-V, but was renamed Libre-SOC following the decision to replace RISC-V with the OpenPOWER 3.0 instruction set architecture (ISA).
The project aims to create a complete, completely open and royalty-free system on a chip (SoC) that can be used in single board computers, netbooks and various portable devices. In addition to CPU-specific instructions and general-purpose registers, Libre-SOC provides the ability to perform vector operations and specialized calculations native to VPUs and GPUs in a single functional block of the processor. The chip uses the OpenPOWER instruction set architecture, the Simple-V extension with instructions for vectorization and data parallel processing, as well as specialized instructions for converting to ARGB and performing typical 3D operations.
GPU instructions are focused on using with the Vulkan graphics API, while VPU is focused on accelerating YUV-RGB conversion and decoding MPEG1/2, MPEG4 ASP (xvid), H.264, H.265, VP8, VP9, AV1, MP3, AC3, Vorbis formats and Opus. A free driver is being developed for Mesa that uses the capabilities of Libre-SOC to provide a hardware-accelerated software implementation of the Vulkan graphics API. For example, Vulkan shaders can be translated with a JIT engine to be executed using custom instructions available in Libre-SOC.
In the next test prototype, they plan to implement the SVP64 (Variable-length Vectorisation) extension, which allows using Libre-SOC as a vector processor (in addition to 32 64-bit general-purpose registers, 128 registers for vector calculations will be provided). The first prototype includes only one core running at 300 Mhz, but within two years it is planned to release a 4-core version, then an 8-core version, and in the long term a 64-core version.
The first batch of the chip will be produced at TSMC using the 180nm process technology. All developments of the project are distributed under free licenses, including files in the GDS-II format with a description of the complete topology of the chip, sufficient to start its own production. Libre-SOC will be the first non-IBM fully independent Power architecture chip. The development used the nMigen hardware description language (Python-based HDL, without the use of VHDL and Verilog), the FlexLib standard cell libraries from the Chips4Makers project, and the free Coriolis2 VLSI toolkit for converting from HDL to GDS-II.
The development of Libre-SOC was funded by the NLnet Foundation, which allocated 400 thousand euros to create a fully open chip as part of a program to create verifiable and trustworthy fundamental technical solutions. The chip has a size of 5.5×5.9 mm and includes 130 logic gates. It includes four 4KB SRAM modules and a 300 MHz phase-locked loop (PLL) unit.
Source: opennet.ru