As we know, the transition to a 3 nm process technology will be accompanied by a transition to a new transistor architecture. In terms of Samsung, for example, these will be MBCFET (Multi Bridge Channel FET) transistors, in which the transistor channel will look like several channels located one above the other in the form of nanopages, surrounded on all sides by a gate (for more details, see ).
According to the developers from the Belgian center Imec, this is a progressive, but not ideal, transistor structure using vertical FinFET gates. Ideal for technical processes with a scale of elements less than 3 nm will be proposed by the Belgians.
Imec developed the split page transistor, or Forksheet. These are the same vertical nanopages as transistor channels, but separated by a vertical dielectric. On one side of the dielectric, a transistor with an n-channel is created, on the other - with a p-channel. And both of them are surrounded by a common gate in the form of a vertical rib.
Reducing the on-chip spacing between transistors of different conductivities is another major challenge for further process downscaling. TCAD simulations confirmed that the split-page transistor would provide a 20 percent reduction in die area. In general, the new transistor architecture will reduce the standard logic cell height to 4,3 tracks. The cell will become simpler, which also applies to the manufacture of the SRAM memory cell.
A simple transition from a nanopage transistor to a single nanopage transistor will provide a 10% increase in performance with the same consumption, or a 24% reduction in consumption without a performance increase. Simulations for the 2nm process showed that a SRAM cell using separate nanopages would provide a combined area reduction and performance improvement of up to 30% with p- and n-junction spacing up to 8 nm.
Source: 3dnews.ru