This morning in Seoul, South Korea, Intel hosted the "Memory and Storage Day 2019" event, dedicated to the future plans for the memory and solid state drives market. At it, company representatives talked about future Optane models, progress in the development of a five-bit PLC NAND (Penta Level Cell) and other promising technologies that it is going to promote over the coming years. Intel also spoke about its desire to introduce non-volatile RAM in desktop computers in the long term and about new models of familiar SSDs for this segment.
The most surprising part of Intel's presentation of ongoing developments was the story of PLC NAND, an even denser form of flash memory. The company emphasizes that over the past two years, the total amount of data produced in the world has doubled, so drives based on four-bit QLC NAND no longer seem like a good solution to this problem - the industry needs some options with more information storage density. The output should be Penta-Level Cell (PLC) flash memory, each cell of which stores five bits of data at once. Thus, the hierarchy of flash memory types will soon look like SLC-MLC-TLC-QLC-PLC. The new PLC NAND will be able to store five times more data compared to SLC, but, of course, with less performance and reliability, since in order to write and read five bits, the controller will have to distinguish between 32 different states of charge of the cell.
It is worth noting that Intel is not alone in its desire to make even denser flash memory. Toshiba also spoke about plans to create PLC NAND during the Flash Memory Summit held in August. However, Intel's technology has significant differences: the company uses floating-gate memory cells, while Toshiba's designs are built around cells based on a charge trap. A floating gate seems to be the best solution with increasing storage density, since it minimizes the mutual influence and flow of charges in the cells and makes it possible to read data with fewer errors. In other words, the Intel design is better suited for increasing density, as evidenced by the test results of commercially available QLC NAND made using different technologies. Such tests show that data degradation in QLC cells based on a floating gate is two to three times slower than in QLC NAND cells with a charge trap.
Against this background, the information that Micron decided to share its flash memory developments with Intel looks quite interesting, including because of the desire to switch to using charge-trap cells. Intel, on the other hand, remains committed to the original technology and systematically implements it in all new solutions.
In addition to PLC NAND, which is still under development, Intel intends to increase the storage density of information in flash memory using other, more affordable technologies. In particular, the company confirmed the imminent transition to the mass production of 96-layer QLC 3D NAND: it will be used in a new consumer drive .
This will be followed by the development of the production of 144-layer QLC 3D NAND - it will fall into mass-produced drives next year. Curiously, however, Intel has so far denied intentions to use triple βsolderingβ monolithic dies, so while the 96-layer design involves vertical assembly of two 48-layer dies, the 144-layer technology will apparently be based on 72-layer "semi-finished products".
Along with the growth in the number of layers in QLC 3D NAND crystals, Intel developers do not intend to increase the capacity of the crystals themselves yet. Based on the 96- and 144-layer technologies, the same terabit crystals as the first generation 64-layer QLC 3D NAND will be produced. This is due to the desire to provide an SSD based on it with an acceptable level of performance. The first SSDs to use 144-layer memory will be Arbordale+ server drives.
Source: 3dnews.ru