IBM discovers developments related to the A2O POWER processor

IBM company announced on the transfer to the OpenPOWER community of the A2O POWER processor core and the FPGA environment for simulating the operation of the reference processor based on it. A2O POWER related documentation, schematics and hardware block descriptions in Verilog and VHDL languages published on GitHub under CC-BY 4.0 license.

Additionally, it is reported that the toolkit will be transferred to the OpenPOWER community Open-CE (Open Cognitive Environment) based on IBM PowerAI. Open-CE provides a collection of tweaks, recipes, and scripts to make it easy to build and deploy machine learning systems based on frameworks like TensorFlow and PyTorch by packaging or containerizing images to run on the Kubernetes platform. Prior to this, in the hands of the OpenPOWER community was transferred Power instruction set architecture (ISA) and processor-related specifications A2I POWER.

The A2O POWER processor core is designed for embedded systems on a chip (SoC), supports out-of-order execution and scheduling, provides multi-threading (2 SMT threads), has GSHARE-like branch prediction, and provides a 64-bit Power 2.07 Book III instruction set architecture -E. A2O continues to develop earlier open A2I kernel in the area of ​​optimizing the performance of individual threads and uses a similar modular design and node interaction structure.

The modular design includes an MMU, a microcode execution engine, and an AXU (Auxiliary Execution Unit) accelerator connection interface, which allows you to create specialized A2O-based solutions optimized for various types of workload, for example, to accelerate machine learning operations.

Source: opennet.ru