As you know, the curator of the PCI Express interface, the interindustrial group PCI-SIG, is in a hurry to make up for the long lag behind the schedule in bringing to market a new version of the PCI Express bus using specifications version 5.0. The final version of the PCIe 5.0 specifications has been approved by this , and in the new year devices with support for the updated bus should appear on the market. Let us remind you that, compared to PCIe 4.0, the transfer speed along the PCIe 5.0 line will double to 32 gigatransactions per second (32 GT/s).
Specifications are specifications, but for the practical implementation of the new interface, working silicon and blocks are needed for licensing to third-party controller developers. One of these decisions yesterday and today at a conference in Taipei companies Astera Labs, Synopsys and Intel. It is claimed that this is the first comprehensive solution that is fully ready for implementation in production and for licensing.
The platform shown in Taiwan uses Intel's pre-production chip, Synopsys DesignWare controller and the company's PCIe 5.0 physical layer, which can be purchased under license, as well as retimers from Astera Labs. Retimers are chips that restore the integrity of clock pulses in the presence of interference or in the event of a weak signal.
As you can imagine, as the speed of data transmission on one line increases, the signal integrity tends to decrease as the communication lines lengthen. For example, according to the specifications for the PCIe 4.0 line, the transmission range without using connectors on the line is only 30 cm. For the PCIe 5.0 line, this distance will be even shorter and even at such a distance it is necessary to include retimers in the controller circuit. Astera Labs managed to develop retimers that can operate both in the PCIe 4.0 interface and as part of the PCIe 5.0 interface, which was demonstrated at the conference.
Source: 3dnews.ru