The LLVM project introduced the release of the HPVM 2.0 (Heterogeneous Parallel Virtual Machine) compiler, aimed at simplifying programming for heterogeneous systems and providing tools for generating code for CPUs, GPUs, FPGAs, and domain-specific hardware accelerators. The project code is distributed under the Apache 2.0 license.
Programming for heterogeneous parallel systems is complicated due to the presence in one system of components that use different models for achieving parallelism (CPU cores, vector instructions, GPUs, etc.), different sets of instructions, and different memory hierarchies. Each system uses its own combination of these components. The main idea of ββthe HPVM project is to use in compiling a unified representation of parallel programs that can be used for various types of hardware that supports parallel computing, including GPUs, vector instructions, multi-core processors, FPGAs, and various specialized accelerator chips.
Unlike other systems, HPVM tried to combine three possibilities for organizing heterogeneous computing - an intermediate representation (IR), a virtual instruction set architecture (V-ISA), and runtime scheduling, independent of the programming language and equipment:
- Intermediate representation HPVM extends the intermediate representation of LLVM instructions by using a hierarchical data flow graph to capture parallelism at the level of tasks, data, and computational pipelines. The HPVM intermediate representation also includes vector instructions and shared memory. The main purpose of using an intermediate representation is efficient code generation and optimization for heterogeneous systems.
- Virtual Instruction Set Architecture (V-ISA) abstracts low-level hardware and unifies various forms of parallelism and memory architectures using only the underlying concurrency model, the Data Flow Graph. V-ISA allows to achieve portability between different types of hardware for parallel computing and makes it possible not to lose performance when using different elements of heterogeneous systems. Virtual ISA can also be used to deliver generic program executable code that can run on CPUs, GPUs, FPGAs, and various accelerators.
- Flexible computing process scheduling policies are applied at runtime and are implemented both on the basis of information about the program (graph structure) and by compiling individual program nodes for execution on any of the target computing devices available in the system.
The code generators developed by the project are capable of translating application nodes defined using virtual ISA for execution using NVIDIA GPUs (cuDNN and OpenCL), Intel AVX vector instructions, FPGAs, and multi-core x86 CPUs. It is noted that the performance of the results of the HPVM translators is comparable to manually written OpenCL code for GPUs and vector computing devices.
Main innovations of HPVM 2.0:
- The Hetero-C++ language frontend is proposed, which simplifies the parallelization of C/C++ application code for compilation in HPVM. Hetero-C++ defines extensions for data-level parallelism and hierarchical tasks that are mapped to HPVM thread graphs.
- An FPGA backend has been added to support code execution on an Intel FPGA. To organize the execution, the Intel FPGA SDK for OpenCL is used.
- The DSE (Design Space Exploration) framework has been added, which includes compiler optimizations and bottleneck detection mechanisms for automatically tuning applications for a given hardware platform. The framework contains a ready-made performance model for FPGA from Intel and allows you to connect your own processors for optimization for any device supported by HPVM. Optimizations can be applied both at the HPVM dataflow graph level and at the LLVM level.
- LLVM components updated to version 13.0.
- The code has been reorganized to make it easier to navigate through the codebase, libraries, and utilities.
- The infrastructure for testing has been improved, new tests have been added for various HPVM components.
Source: opennet.ru