The VeriGPU project aims to create an open GPU developed in the Verilog electronic systems description and modeling language. Initially, the project is being developed using the Verilog simulator, but after bringing it to readiness, it can be used to produce real chips. Project developments are distributed under the MIT license.
The VeriGPU is positioned as an Application Specific Processing Unit (ASIC) optimized to accelerate computations related to machine learning systems. The plans mention providing compatibility with the PyTorch deep machine learning framework and the possibility of developing applications for the VeriGPU using the HIP (Heterogeneous-Compute Interface) API. In the future, the addition of support for other APIs, such as SYCL and NVIDIA CUDA, is not ruled out.
The GPU evolves based on the RISC-V instruction set, but the resulting internal architecture of the GPU instruction set is poorly compatible with the RISC-V ISA, since in situations where the design of the GPU does not fit into the RISC-V representation, the task of maintaining compatibility with RISC-V is not set. . The development is focused on the capabilities needed for machine learning systems, therefore, to reduce the size and complexity of the chip matrix, only the BF16 floating point format is used, and only floating point operations that are in demand for machine learning, such as exp, log, tanh and sqrt, are available.
Of the already available components, the GPU controller, APU (Accelerated Processing Unit) for integer operations (β+β, β-β, β/β, β*β), block for floating point operations (β+β, β*β) and a branching unit. To create applications, an assembler and support for compiling C++ code based on LLVM are offered. Of the planned features, parallel execution of instructions, caching of data and instruction memory, SIMT operations (Single instruction multiple thread) stand out.
Source: opennet.ru