Certifying body checks all new products that are preparing to enter the market for compliance with the requirements of the PCI Express 3.0 standard. Recently, an entry appeared in the profile database about the successful certification of Intel Lakefield processors. This once again proves that they are close to entering the market. An Intel presentation published in August promised that mass production of Lakefield processors would start at the end of the year. In December, a company executive added that Lakefield processors will be among the first to use the next-generation 10nm process technology.
Recall that Lakefield processors will simultaneously use the Foveros spatial layout, which will allow several heterogeneous components, including RAM, to be placed in five tiers. All this diversity will fit in a 12 Γ 12 Γ 1 mm package, which will allow the use of Lakefield processors in compact mobile devices. For example, one of the Microsoft Surface Neo models, which is a foldable tablet with two displays, will use Lakefield processors.
Support for PCI Express 3.0, according to the layout sketches of Lakefield processors, should be provided by the lower layer of silicon, produced using 22-nm technology. Computing cores will be located in a separate layer, which will be produced using 10 nm++ class technology. Four compact cores with Tremont architecture will be adjacent to one performance core with Sunny Cove microarchitecture, next to it there will be a Gen11 graphics subsystem with 64 execution units.
It is noteworthy that at the end of next year, Intel plans to update Lakefield processors. By that time, 4.0nm Tiger Lake processors may provide PCI Express 10 support in the client segment, it is possible that Lakefield Refresh processors will follow suit.
Source: 3dnews.ru