After a year of development, the release of the free GCC 12.1 compiler suite has been published, the first significant release in the new GCC 12.x branch. Under the new release numbering scheme, version 12.0 was used during development, and shortly before the release of GCC 12.1, the GCC 13.0 branch was already forked, from which the next significant release of GCC 13.1 will form. On May 23, the project will celebrate 35 years since the formation of the first release of GCC.
Major changes:
- Added support for the CTF (Compact Type Format) debugging format, which provides compact storage of information about C-types, relationships between functions and debugging symbols. When embedded in ELF objects, the format allows the use of EFL symbol tables to avoid data duplication.
- Deprecated support for the "STABS" debug information storage format, created in the 1980s.
- Work continues to expand support for future C2X and C++23 standards for C and C++. For example, support for the "if consteval" statement has been added; allowed to use auto in function arguments ("f(auto(g()))"); allowed the use of non-literal variables, goto and labels in functions declared as constexpr; added support for multidimensional index operators operator[]; in if, for and switch, the capabilities of initialization blocks are extended ("for (using T = int; T e : v)").
- Support for the experimental sections of the C++20 and C++23 standards has been improved in the C++ Standard Library. Added support for std::move_only_function, , std::basic_string::resize_and_overwrite, , and std::invoke_r. The use of std::unique_ptr, std::vector, std::basic_string, std::optional, and std::variant in constexpr functions is allowed.
- The Fortran front-end provides full support for the TS 29113 specification, which describes the possibilities for ensuring portability between Fortran and C code.
- Added support for the __builtin_shufflevector(vec1, vec2, index1, index2, β¦) extension previously added to Clang, which offers a single call to perform common vector shuffle and shuffle operations.
- When using the "-O2" optimization level, vectorization is enabled by default (the -ftree-vectorize and -fvect-cost-model=very-cheap modes are enabled). The "very-cheap" model allows vectorization only if the vector code can completely replace the vectorizable scalar code.
- Added "-ftrivial-auto-var-init" mode to enable explicit initialization of variables on the stack to track issues and block vulnerabilities associated with the use of uninitialized variables.
- For C and C++ languages, a built-in function __builtin_dynamic_object_size has been added to determine the size of an object, compatible with a similar function from Clang.
- Support for the "unavailable" attribute has been added for the C and C++ languages ββ(for example, you can mark functions that will result in an error when they are used).
- Added support for "#elifdef" and "#elifndef" preprocessing directives for C and C++ languages.
- Added "-Wbidi-chars" flag to warn if UTF-8 characters are used incorrectly, changing the display order of bidirectional text.
- Added "-Warray-compare" flag to issue a warning when trying to compare two operands that refer to arrays.
- The implementation of the OpenMP 5.0 and 5.1 (Open Multi-Processing) standards, which define the API and methods for applying parallel programming methods on multi-core and hybrid (CPU + GPU / DSP) systems with shared memory and vectorization units (SIMD), was continued.
- Improved implementation of the OpenACC 2.6 parallel programming specification, which defines tools for offloading operations on GPUs and specialized processors such as NVIDIA PTX.
- Added support for Intel AVX86-FP512 extended instructions and the _Float16 type to the x16 code generation backend.
- For the x86 architecture, added protection against vulnerabilities in processors caused by speculative execution of instructions after unconditional forward jump operations. The problem arises from the preemptive processing of instructions immediately following the branch instruction in memory (SLS, Straight Line Speculation). To enable protection, the "-mharden-sls" option is proposed.
- Added a definition for the use of uninitialized variables to the experimental static analyzer. Added initial support for analyzing assembler code in inline inserts. Improved memory tracking. Rewritten code for processing switch expressions.
- Added 30 new calls to libgccjit, a shared library for embedding a code generator in other processes and using it to JIT bytecode compilation to native code.
- Support for the CO-RE (Compile Once - Run Everywhere) mechanism has been added to the backend for generating BPF bytecode, which allows compiling the code of eBPF programs for the Linux kernel only once and using a special universal loader that adapts the loaded program to the current kernel and BTF types (BPF Type format). CO-RE solves the problem with the portability of compiled eBPF programs that could previously only be used in the version of the kernel for which they were built, since the position of elements in data structures varies from version to version.
- Support for new zba, zbb, zbc, and zbs instruction set architecture extensions, as well as ISA extensions for vector and scalar cryptographic operations, has been added to the RISC-V backend. Support for the RISC-V ISA 20191213 specification is provided by default. The -mtune=thead-c906 flag has been added to enable optimizations for the T-HEAD c906 cores.
- Support for the __int128_t/integer(kind=16) type has been added to the code generation backend for AMD GPUs based on the GCN microarchitecture. It is possible to use up to 40 workgroups per computing unit (CU) and up to 16 instruction fronts (wavefront, a set of threads executed in parallel by the SIMD Engine) per group. Previously, only one instruction edge per CU was allowed.
- The NVPTX backend, designed to generate code using the NVIDIA PTX (Parallel Thread Execution) instruction set architecture, has added the ability to use the "-march", "-mptx" and "-march-map" flags. Implemented support for PTX ISA sm_53, sm_70, sm_75 and sm_80. The default architecture is sm_30.
- Implementations of built-in functions have been rewritten in the backend for PowerPC / PowerPC64 / RS6000 processors. The built-in functions __builtin_get_texasr, __builtin_get_texasru, __builtin_get_tfhar, __builtin_get_tfiar, __builtin_set_texasr, __builtin_set_texasru, __builtin_set_tfhar and __builtin_set_tfiar are documented.
- Added support for Arm Ampere-64 (-mcpu/-mtune ampere1), Arm Cortex-A1 (cortex-a510), Arm Cortex-A510 (cortex-a710), and Arm Cortex-X710 (cortex- x2). Added support for new ARMv2 architecture variants for use in the "-march" option: armv8-a, armv8.7-a, armv8.8-a. Implementation of C-functions built into the compiler (Intrinsics) for atomic loading and saving data into memory, based on the use of extended ARM instructions (ls9), has been added. Added support for accelerating the memcpy, memmove and memset functions using the mopsoption ARM extension.
- A new check mode "-fsanitize=shadow-call-stack" (ShadowCallStack) has been added, which is currently only available for the AArch64 architecture and works when building code with the "-ffixed-r18" option. The mode provides protection against rewriting the return address from the function in case of buffer overflow on the stack. The essence of protection is to save the return address in a separate βshadowβ stack after transferring control to the function and extract this address before exiting the function.
Source: opennet.ru