Last night, a technical document surfaced on the Web describing some of the characteristics of the expected Ryzen 4000 processors built on the Zen 3 microarchitecture. In general, it did not bring any special revelations, but it did confirm many of the assumptions that were made earlier.
According to the documentation, the Ryzen 4000 processors (codename Vermeer) will retain the chiplet layout introduced in their predecessors of the Zen 2 generation. Future mass processors, as it was before, will have an I / O chiplet and one or two CCDs (Core Complex Die) - chiplets containing computing cores.
The key difference between Zen 3 processors will be the internal structure of the CCD. While now each CCD contains two quad-core CCXs (Core Complex), each of which has its own 3 MB L16 cache segment, the Ryzen 4000 chiplets will consist of one eight-core CCX. The volume of the L3 cache in each CCX will be increased from 16 to 32 MB, but this, obviously, will not lead to a change in the total capacity of the cache memory. Octa-core Ryzen 4000 series processors, which will now have a single CCD chip, will have a 32MB L3 cache, while 16-core CPUs with two CCD chips will have a 64MB L3 cache composed of two segments.
There is no need to wait for changes in the volume of the L2 cache: each of the processor cores will have 512 KB of LXNUMX cache.
However, scaling up the CCX will have an obvious impact on performance. Each of the cores in Zen 3 will have direct access to a larger portion of the third level cache, and in addition, more cores will be able to communicate directly, bypassing the Infinity Fabric. This means that Zen 3 will reduce inter-core communication latencies and reduce the impact on performance of the limited bandwidth of the connecting part of the Infinity Fabric bus processor, which means that IPC (the number of instructions executed per clock) will eventually increase.
At the same time, we are not talking about any increase in the number of cores in consumer processors. The maximum number of CCD chips in the Ryzen 4000 will be limited to two, so the maximum number of cores in the processor will not be able to step over 16.
Also, no fundamental changes with memory support are foreseen. As follows from the document, DDR4000-4 will remain the maximum officially supported mode for the Ryzen 3200.
The documentation does not provide any details about the composition of the model range and the frequencies of the processors included in it. More details will obviously be revealed on October 8, when AMD will hold a special event dedicated to Ryzen 4000 processors and the Zen 3 microarchitecture.
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Source: 3dnews.ru