Today, Samsung Electronics on plans for the development of technical processes for the production of semiconductors. The company considers the creation of digital projects of experimental 3-nm chips based on patented MBCFET transistors as the main current achievement. These are transistors with many horizontal nanopage channels in vertical FET gates (Multi-Bridge-Channel FET).
As part of an alliance with IBM, Samsung was developing a slightly different technology for the production of transistors with channels completely surrounded by gates (GAA or Gate-All-Around). The channels were supposed to be made thin in the form of nanowires. Subsequently, Samsung moved away from this scheme and patented the structure of transistors with channels in the form of nanopages. This structure allows you to control the characteristics of transistors by manipulating both the number of pages (channels) and adjusting the width of the pages. For classical FET technology, such a maneuver is impossible. To increase the power of a FinFET transistor, it is necessary to multiply the number of FET fins on the substrate, and this is the area consumption. The characteristics of the MBCFET transistor can be changed within one physical gate, for which you need to set the width of the channels and their number.
The availability of a digital project (taped out) of a prototype chip for release using the GAA manufacturing process allowed Samsung to define the limits of the MBCFET transistors. It should be borne in mind that this is still computer simulation data and it will be possible to finally judge the new technical process only after it is launched into mass production. However, there is a starting point. The company said that the transition from the 7nm process technology (obviously the first generation) to the GAA process technology will provide a reduction in die area by 45% and a reduction in consumption by 50%. If you do not save on consumption, then productivity can be increased by 35%. Previously, Samsung saves and increases performance when moving to a 3-nm process through a comma. It turned out to be either one or the other.
The company considers the preparation of a public cloud platform for independent chip developers and factoryless companies to be an important point for popularizing the 3nm process technology. Samsung did not hide the development environment, project reviews and libraries on production servers. The SAFE (Samsung Advanced Foundry Ecosystem Cloud) platform will be available to designers around the world. The SAFE cloud platform was built with the participation of major public cloud services such as Amazon Web Services (AWS) and Microsoft Azure. Design tools from Cadence and Synopsys provided SAFE design tools. This promises to make it easier and cheaper to create new solutions for Samsung's process technology.
Returning to Samsung's 3nm process technology, the company has released the first version of its chip development kit, 3nm GAE PDK Version 0.1. With its help, today you can start designing 3nm solutions, or at least prepare for meeting this Samsung process technology when it becomes mass.
Samsung announces further plans as follows. In the second half of this year, mass production of chips using a 6-nm process technology will be launched. At the same time, the development of a 4-nm process technology will be completed. Development of the first Samsung products using the 5nm process will be completed this fall, with production in the first half of next year. Also, by the end of this year, Samsung will complete the development of the 18FDS process technology (18 nm on FD-SOI wafers) and 1-Gb eMRAM chips. Process technologies from 7nm to 3nm will use EUV scanners at an increasing rate, and every nanometer counts. Further down the path, each step will be made with a fight.
Source: 3dnews.ru