As we know, in March of this year, TSMC began the pilot production of 5nm products. This happened at the new Fab 18 factory in Taiwan, for the release of 5-nm solutions. Mass production using the 5nm N5 process is expected in the second quarter of 2020. Until the end of the same year, the production of chips based on the productive 5nm process technology or N5P (performance) will be launched. The presence of experimental chips allows TSMC to evaluate the capabilities of future semiconductors released on the basis of a new process technology, which the company will talk about in detail in December. But there are some things you can already know. from abstract submissions submitted by TSMC to speak at IEDM 2019.
Before getting into the details, let's recap what we know from previous TSMC announcements. It is claimed that compared to the 7nm process, the net performance of 5nm chips will increase by 15% or consumption will decrease by 30% if the performance is left the same. The N5P process will add another 7% performance or 15% savings in consumption. The density of logical elements placement will increase by 1,8 times. The scale of the SRAM cell will change to 0,75 times.
In the production of 5nm chips, the scale of use of EUV scanners will reach the level of mature production. The transistor channel structure will be changed, perhaps by using germanium together with or instead of silicon. This will provide an increased mobility of electrons in the channel and an increase in currents. The process technology provides several levels of control voltages, the highest of which will give a performance increase of 25% compared to the same in the 7nm process technology. The transistor power supply for the I/O interfaces will be between 1,5 V and 1,2 V.
Materials with even lower resistance will be used in the production of through holes for plating and for contacts. For the manufacture of ultra-high-density capacitors, a metal-dielectric-metal circuit will be used, which will increase productivity by 4%. In general, TSMC will switch to using new low-K insulators. A new βdryβ Metal Reactive Ion Etching (RIE) process will appear in the silicon wafer processing scheme, which will partially replace the traditional Damascus process using copper (for metal contacts smaller than 30 nm). Also, for the first time, a layer of graphene will be used to create a barrier between copper conductors and a semiconductor (to prevent electromigration).
From the documents for the December report at IEDM, we can learn that a number of parameters of 5nm chips will turn out to be even better. Thus, the placement density of logic elements will be higher and reach 1,84 times. The SRAM cell will also be smaller, with an area of ββ0,021 Β΅m2. With the performance of the experimental silicon, everything is in order - a 15% increase was obtained, as well as a 30% decrease in consumption in the case of freezing the high frequencies.
The new manufacturing process will provide a choice of seven control voltages, which will add variety to the development process and products, and the use of EUV scanners will definitely simplify and make production cheaper. According to TSMC, the transition to EUV scanners provides a 0,73x improvement in linear resolution over the 7nm process. For example, for the manufacture of the most critical metallization layers of the first layers, instead of five conventional masks, only one EUV mask is required and, accordingly, only one technological cycle instead of five. By the way, pay attention to how accurate the elements on the crystal turn out when using the EUV projection. Beauty, and only.
Source: 3dnews.ru