Rostec State Corporation and technology company Yadro (ICS Holding) intend to develop and start production of a new processor for laptops, PCs and servers based on the RISC-V architecture by 2025. Computers based on the new processor are planned to equip workplaces in Rostec divisions and institutions of the Ministry of Education and Science, the Ministry of Education and the Ministry of Health of the Russian Federation. The project will invest 27,8 billion rubles (including 9,8 billion from the federal budget), which is more than the total investment in the production of Elbrus and Baikal processors. In accordance with the business plan, in 2025 they plan to sell 60 complexes based on new processors and earn 7 billion rubles for this.
Yadro, a server and storage company, has owned Syntacore since 2019, which is one of the oldest developers of specialized open and commercial RISC-V IP cores (IP Core), and is also a founding member of the non-profit organization RISC-V International who oversees the development of the RISC-V instruction set architecture. Thus, there are more than enough resources, experience and competence to create a new RISC-V chip.
It is reported that the developed chip will include an 8-core processor operating at a frequency of 2 GHz. It is planned to use the 12nm manufacturing process for production (for comparison, in 2023, Intel plans to produce a chip based on the SiFive P550 RISC-V core using 7 nm technology, and in 2022, China is expected to produce the XiangShan chip, also operating at a frequency of 2 GHz, using the manufacturing process 14 nm).
Currently, Syntacore already offers a RISC-V SCR7 core for licensing that is suitable for use in consumer computers and supports the use of Linux-based systems. The SCR7 implements the RV64GC RISC-V instruction set architecture and includes a virtual memory controller with memory page support, an MMU, L1/L2 caches, a floating point unit, three privilege levels, AXI4- and ACE-compliant interfaces, and SMP support (up to 8 nuclei).
As for the software stuffing, RISC-V support is being successfully developed in Debian GNU/Linux. In addition, at the end of June, Canonical announced the formation of ready-made builds of Ubuntu 20.04 LTS and 21.04 for SiFive HiFive Unmatched and SiFive HiFive Unleashed RISC-V boards. RISC-V has also recently been ported to the Android platform. Notably, Yadro has been a silver member of the Linux Foundation since 2017 and is also a member of the OpenPOWER Foundation consortium that promotes the OpenPOWER instruction set architecture (ISA).
Recall that RISC-V provides an open and flexible system of machine instructions that allows you to create microprocessors for arbitrary applications, without requiring royalties and without imposing conditions on use. RISC-V allows the creation of completely open SoCs and processors. Currently, based on the RISC-V specification, various companies and communities under various free licenses (BSD, MIT, Apache 2.0) are developing several dozen variants of microprocessor cores, SoCs, and already manufactured chips. Operating systems with good RISC-V support include GNU/Linux (present since Glibc 2.27, binutils 2.30, gcc 7, and the Linux 4.15 kernel) and FreeBSD.
Source: opennet.ru