The release of the CoreBoot 4.22 project is available, within the framework of which a free alternative to proprietary firmware and BIOS is being developed. The project code is distributed under the GPLv2 license. 135 developers took part in the creation of the new version, who prepared 977 changes. It is noted that starting from the next release, the project will switch to a new version naming scheme that uses a date reference (year.month.update), for example, in February 2024, instead of version 4.23, release 24.02.00 will be formed.
Major changes:
- An initial implementation of the AMD openSIL (Open-Source Silicon Initialization Library) platform has been added, developing components to simplify the creation of firmware.
- Added support for 17 motherboards. 11 of the added boards are used on devices running Chrome OS or серверах Google. Non-Google related fees:
- AMD Onyx
- Intel Meteorlake-P RVP
- Purism Librem 11
- Purism Librem L1UM v2
- Siemens FA EHL
- Supermicro X11SSW-F
- Added support for AMD Genoa SoC.
- On the x86 architecture, at the stages before memory initialization, support for the “.data” section is implemented, allowing the use of definitions of global variables in C code. During the load block stage, data is attached immediately after the code and then placed in the cache using the Cache-As-RAM (VMA) concept.
- For x86 systems at the ramstage and pre-memory stages, cache support has been implemented for the CBFS file system used to host Coreboot components on Flash. The CBFS cache allows you to decompress CBFS files using the cbfs_map() function without reserving a separate memory area for the file. To configure the cache size, the PRERAM_CBFS_CACHE_SIZE and RAMSTAGE_CBFS_CACHE_SIZE parameters are proposed.
- Added the ability to embed romstage into the bootblock. Delivery of romstage as part of the boot block allows you to reduce the code size by 10-20 thousand lines. Situations in which a separate romstage may be required include configurations with vboot or fallback mode, as well as devices with a limited boot block size (Intel APL 32K) or too slow boot media (some ARM SoCs).
- An API has been added to gfx to detect the presence of an external screen on devices with Intel chips.
- pci_rom now supports adding a checksum for the VBIOS when populating the VFCT table. This checksum is also checked by some AMD drivers for Windows.
- Added changes to allow launching Windows on some Chromebooks with Coreboot.
- Implemented ACPI table generation for devices based on ARM64 architecture.
- Improved compatibility with ACPI specifications.
- MRC (Memory Reference Code) settings for SNB+MRC boards have been moved to the DeviceTree structure.
- Updated payload components based on U-Boot and edk2.
- The tools used have been updated: GMP 6.3.0, binutils 2.41 and MPFR 4.2.1.
- The main branch in the Git repository has been renamed from “master” to “main”.
Source: opennet.ru
