{"id":102428,"date":"2021-11-30T15:36:39","date_gmt":"2021-11-30T13:36:41","guid":{"rendered":"https:\/\/prohoster.info\/blog\/novosti-interneta\/vortex-otkrytyj-gpgpu-na-baze-arhitektury-risc-v-sovmestimyj-s-opencl"},"modified":"2021-11-30T15:36:39","modified_gmt":"2021-11-30T13:36:41","slug":"vortex-otkrytyj-gpgpu-na-baze-arhitektury-risc-v-sovmestimyj-s-opencl","status":"publish","type":"post","link":"https:\/\/prohoster.info\/en\/blog\/news\/vortex-otkrytyj-gpgpu-na-baze-arhitektury-risc-v-sovmestimyj-s-opencl","title":{"rendered":"Vortex \u2014 an open GPGPU based on RISC-V architecture, compatible with OpenCL","gt_translate_keys":[{"key":"rendered","format":"text"}]},"content":{"rendered":"
A team of researchers from the Georgia Institute of Technology is developing the Vortex research project, which offers an open GPGPU based on the RISC-V instruction set architecture, aimed at executing parallel computations using the OpenCL API and the SIMT (Single Instruction, Multiple Threads) execution model, as well as conducting research in 3D graphics and developing new GPU architectures. The project is currently at the prototype stage, operating with FPGA. Schematics, hardware block descriptions in Verilog, simulator, drivers, and related project documentation are distributed under the BSD license. <\/p>\n
In its current form, a standard RISC-V ISA is provided, extended with some additional instructions necessary for supporting GPU functions and stream management. In development, the authors of the project aimed to minimize changes to the RISC-V instruction set architecture, utilizing existing vector instructions whenever possible. A similar approach is also applied in the RV64X project, which also develops an open GPU based on RISC-V technologies.
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The graphics processing capabilities of Vortex are currently limited. Support for OpenGL ES has been announced for Vortex, but the GPU only has the «tex» instruction implemented for accelerating texture processing, which is carried out at the fragment shader level. A built-in rasterizer is absent \u2014 all geometric operations are processed on the system CPU, while basic primitives for points, lines, and triangles, as well as fragment processing, depth, and transparency, are handled using OpenCL.
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In the future, it is planned to implement graphics-specific ISA extensions, add support for CUDA and Vulkan APIs, as well as extensions for accelerating machine learning systems and data analytics. For application development, a toolkit is offered, including adapted versions of PoCL (OpenCL compiler and runtime), LLVM\/Clang, GCC, and Binutils for working with Vortex. Chip operation simulation is supported using Verilator (Verilog simulator) and SimX (software simulation).
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Key features of Vortex: <\/p>\n
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Support for the RISC-V RV32IMF instruction set architecture.\n
Chip scaling up to 64 cores with optional L2 and L3 caches.\n
Each core can execute 1024 threads and operate at a frequency of 250 MHz.\n
The maximum computing power is estimated at 128 Gflops, with a memory bandwidth of 16 GB\/s. A 32-core implementation running at 200 MHz on an Altera Stratix 10 FPGA demonstrated a performance of 25.6 GFlops.\n
Support for the OpenCL 1.2 standard.\n
Implementation capability based on Intel Arria 10 and Intel Stratix 10 FPGAs. <\/ul>\n
![\"Vortex](\"\/wp-content\/uploads\/2021\/11\/b28015da9f9188f87f402a8b14ee070b.jpg\")
<\/center> <\/p>\n![\"Vortex](\"\/wp-content\/uploads\/2021\/11\/a12215387481ff353fb2fd4454c286da.jpg\")
<\/center> <\/p>\n![\"Vortex](\"\/wp-content\/uploads\/2021\/11\/d0b801f648a6863f190ec62c4a36fb6a.jpg\")
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