{"id":103469,"date":"2022-03-03T15:36:38","date_gmt":"2022-03-03T13:36:39","guid":{"rendered":"https:\/\/prohoster.info\/blog\/novosti-interneta\/intel-amd-i-arm-predstavili-ucie-otkrytyj-standart-dlya-chipletov"},"modified":"2022-03-03T15:36:38","modified_gmt":"2022-03-03T13:36:39","slug":"intel-amd-i-arm-predstavili-ucie-otkrytyj-standart-dlya-chipletov","status":"publish","type":"post","link":"https:\/\/prohoster.info\/en\/blog\/news\/intel-amd-i-arm-predstavili-ucie-otkrytyj-standart-dlya-chipletov","title":{"rendered":"Intel, AMD, and ARM have introduced UCIe, an open standard for chiplets.","gt_translate_keys":[{"key":"rendered","format":"text"}]},"content":{"rendered":"
The formation of the UCIe (Universal Chiplet Interconnect Express) consortium has been announced, aimed at developing open specifications and creating an ecosystem for chiplet technology. Chiplets allow for the creation of combined hybrid integrated circuits (multi-chip modules) made up of independent semiconductor blocks that are not tied to a single manufacturer and interact with each other using the standard high-speed UCIe interface.
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To develop a specialized solution, such as creating a processor with an embedded accelerator for machine learning or processing network operations, it is sufficient to utilize existing chiplets with processing cores or accelerators offered by different manufacturers. If standard solutions are not available, one can create a custom chiplet with the required functionality, employing preferred technologies and solutions. <\/p>\n
After that, it is enough to combine the selected chiplets using a block layout similar to LEGO builders (the proposed technology somewhat resembles the use of PCIe boards for assembling a computer's internals, but at the integrated circuit level). Data exchange and interaction between chiplets are carried out using the high-speed UCIe interface, and the blocks are assembled using the 'system-on-package' (SoP) paradigm instead of 'system-on-chip' (SoC). <\/p>\n
Compared to SoC, the chiplet technology allows for the creation of interchangeable and reusable semiconductor blocks that can be used in different devices, significantly reducing chip development costs. In systems based on chiplets, various architectures and manufacturing processes can be combined \u2014 since each chiplet operates independently, interacting through standard interfaces, blocks with different instruction set architectures (ISAs), such as RISC-V, ARM, and x86, can coexist in a single product. The use of chiplets also simplifies testing \u2014 each chiplet can be tested separately before integration into the final solution.
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Intel, AMD, ARM, Qualcomm, Samsung, ASE (Advanced Semiconductor Engineering), Google Cloud, Meta\/Facebook, Microsoft, and Taiwan Semiconductor Manufacturing Company have joined the initiative to promote chiplet technology. An open specification UCIe 1.0 has been presented to the public, standardizing methods for interconnecting integrated circuits on a common basis, a protocol stack, a software model, and a testing process. The interfaces for connecting chiplets announced support for PCIe (PCI Express) and CXL (Compute Express Link). \n Source: opennet.ru<\/a> <\/p>","protected":false,"gt_translate_keys":[{"key":"rendered","format":"html"}]},"excerpt":{"rendered":"
![\"Intel,](\"\/wp-content\/uploads\/2022\/03\/df0a0fc13f353218153a6a7017a9df14.jpg\")
<\/center> <\/p>\n![\"Intel,](\"\/wp-content\/uploads\/2022\/03\/35be0baf53df78c988a109496152cf89.jpg\")
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