{"id":103860,"date":"2022-04-23T21:36:37","date_gmt":"2022-04-23T19:36:38","guid":{"rendered":"https:\/\/prohoster.info\/blog\/novosti-interneta\/proekt-verigpu-razvivaet-otkrytyj-gpu-na-yazyke-verilog"},"modified":"2022-04-23T21:36:37","modified_gmt":"2022-04-23T19:36:38","slug":"proekt-verigpu-razvivaet-otkrytyj-gpu-na-yazyke-verilog","status":"publish","type":"post","link":"https:\/\/prohoster.info\/en\/blog\/news\/proekt-verigpu-razvivaet-otkrytyj-gpu-na-yazyke-verilog","title":{"rendered":"The VeriGPU project is developing an open GPU using Verilog.","gt_translate_keys":[{"key":"rendered","format":"text"}]},"content":{"rendered":"

The VeriGPU project aims to create an open GPU developed using the Verilog hardware description and modeling language. Initially, the project is being developed using a Verilog simulator, but once completed, it will be able to be used for the production of real chips. The project\u2019s developments are distributed under the MIT License. <\/p>\n

VeriGPU is positioned as a specialized processor (ASIC) optimized for accelerating computations related to machine learning systems. Plans mention compatibility with the deep learning framework PyTorch and the implementation of application development for VeriGPU using the HIP (Heterogeneous-Compute Interface) API. Future support for other APIs, such as SYCL and NVIDIA CUDA, is also anticipated. <\/p>\n

The GPU is developed based on the RISC-V instruction set; however, the final internal architecture of the GPU instruction set is only loosely compatible with the RISC-V ISA, as the design of the GPU does not aim to maintain compatibility with RISC-V when it does not fit within the RISC-V representation. Development is focused on the capabilities necessary for machine learning systems, which is why only the BF16 floating-point computation format is used to reduce the size and complexity of the chip matrix, and only essential floating-point operations for machine learning, such as exp, log, tanh, and sqrt, are made available. <\/p>\n

The already available components include a GPU controller, APU (Accelerated Processing Unit) for integer operations (+, -, \/, *), a block for floating-point operations (+, *), and a branching unit. The tools for application development include an assembler and support for C++ code compilation based on LLVM. Planned features include parallel instruction execution, caching of data and instruction memory, and SIMT (Single Instruction Multiple Thread) operations.

\"The<\/center>
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Source: opennet.ru<\/a> <\/p>","protected":false,"gt_translate_keys":[{"key":"rendered","format":"html"}]},"excerpt":{"rendered":"

\u041f\u0440\u043e\u0435\u043a\u0442 VeriGPU \u043d\u0430\u0446\u0435\u043b\u0435\u043d \u043d\u0430 \u0441\u043e\u0437\u0434\u0430\u043d\u0438\u0435 \u043e\u0442\u043a\u0440\u044b\u0442\u043e\u0433\u043e GPU, \u0440\u0430\u0437\u0432\u0438\u0432\u0430\u0435\u043c\u043e\u0433\u043e \u043d\u0430 \u044f\u0437\u044b\u043a\u0435 \u043e\u043f\u0438\u0441\u0430\u043d\u0438\u044f \u0438 \u043c\u043e\u0434\u0435\u043b\u0438\u0440\u043e\u0432\u0430\u043d\u0438\u044f \u044d\u043b\u0435\u043a\u0442\u0440\u043e\u043d\u043d\u044b\u0445 \u0441\u0438\u0441\u0442\u0435\u043c Verilog. \u0418\u0437\u043d\u0430\u0447\u0430\u043b\u044c\u043d\u043e \u043f\u0440\u043e\u0435\u043a\u0442 \u0440\u0430\u0437\u0440\u0430\u0431\u0430\u0442\u044b\u0432\u0430\u0435\u0442\u0441\u044f \u0441 \u0438\u0441\u043f\u043e\u043b\u044c\u0437\u043e\u0432\u0430\u043d\u0438\u0435\u043c \u0441\u0438\u043c\u0443\u043b\u044f\u0442\u043e\u0440\u0430 Verilog, \u043d\u043e \u043f\u043e\u0441\u043b\u0435 \u0434\u043e\u0432\u0435\u0434\u0435\u043d\u0438\u044f \u0434\u043e \u0433\u043e\u0442\u043e\u0432\u043d\u043e\u0441\u0442\u0438 \u0441\u043c\u043e\u0436\u0435\u0442 \u0438\u0441\u043f\u043e\u043b\u044c\u0437\u043e\u0432\u0430\u0442\u044c\u0441\u044f \u0434\u043b\u044f \u043f\u0440\u043e\u0438\u0437\u0432\u043e\u0434\u0441\u0442\u0432\u0430 \u0440\u0435\u0430\u043b\u044c\u043d\u044b\u0445 \u0447\u0438\u043f\u043e\u0432. \u041d\u0430\u0440\u0430\u0431\u043e\u0442\u043a\u0438 \u043f\u0440\u043e\u0435\u043a\u0442\u0430 \u0440\u0430\u0441\u043f\u0440\u043e\u0441\u0442\u0440\u0430\u043d\u044f\u044e\u0442\u0441\u044f \u043f\u043e\u0434 \u043b\u0438\u0446\u0435\u043d\u0437\u0438\u0435\u0439 MIT. VeriGPU \u043f\u043e\u0437\u0438\u0446\u0438\u043e\u043d\u0438\u0440\u0443\u0435\u0442\u0441\u044f \u043a\u0430\u043a \u0441\u043f\u0435\u0446\u0438\u0430\u043b\u0438\u0437\u0438\u0440\u043e\u0432\u0430\u043d\u043d\u044b\u0439 \u043f\u0440\u043e\u0446\u0435\u0441\u0441\u043e\u0440 (ASIC), \u043e\u043f\u0442\u0438\u043c\u0438\u0437\u0438\u0440\u043e\u0432\u0430\u043d\u043d\u044b\u0439 \u0434\u043b\u044f \u0443\u0441\u043a\u043e\u0440\u0435\u043d\u0438\u044f \u0432\u044b\u0447\u0438\u0441\u043b\u0435\u043d\u0438\u0439, \u0441\u0432\u044f\u0437\u0430\u043d\u043d\u044b\u0445 \u0441 \u0441\u0438\u0441\u0442\u0435\u043c\u0430\u043c\u0438 \u043c\u0430\u0448\u0438\u043d\u043d\u043e\u0433\u043e \u043e\u0431\u0443\u0447\u0435\u043d\u0438\u044f. […]<\/p>\n","protected":false,"gt_translate_keys":[{"key":"rendered","format":"html"}]},"author":1,"featured_media":103861,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[702],"tags":[],"class_list":["post-103860","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-news"],"aioseo_notices":[],"aioseo_head":"\n\t\t\n\t\n\t\n\t\n\t\n\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\n","aioseo_head_json":{"title":"\ud83e\udd47The VeriGPU project develops an open GPU using Verilog | ProHoster","description":"The VeriGPU project aims to create an open GPU developed using the Verilog hardware description and modeling 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