{"id":111428,"date":"2023-11-11T03:10:14","date_gmt":"2023-11-11T01:10:14","guid":{"rendered":"https:\/\/prohoster.info\/blog\/novosti-interneta\/dostupen-vortex-2-0-otkrytyj-gpgpu-na-baze-arhitektury-risc-v"},"modified":"2023-11-11T03:10:14","modified_gmt":"2023-11-11T01:10:14","slug":"dostupen-vortex-2-0-otkrytyj-gpgpu-na-baze-arhitektury-risc-v","status":"publish","type":"post","link":"https:\/\/prohoster.info\/en\/blog\/news\/dostupen-vortex-2-0-otkrytyj-gpgpu-na-baze-arhitektury-risc-v","title":{"rendered":"Vortex 2.0 is available, an open GPGPU based on the RISC-V architecture.","gt_translate_keys":[{"key":"rendered","format":"text"}]},"content":{"rendered":"
The second edition of the Vortex project has been published, which develops an open GPGPU based on the RISC-V instruction set architecture, designed for performing parallel computations using the OpenCL API and the SIMT (Single Instruction, Multiple Threads) execution model. The project can also be used for research in 3D graphics and the development of new GPU architectures. Schemas, hardware block descriptions in Verilog, simulators, drivers, and associated project documentation are distributed under the Apache 2.0 license. <\/p>\n
The core of GPGPU is a typical RISC-V ISA, extended by some additional instructions necessary to support GPU functions and manage threads. At the same time, changes to the RISC-V instruction set architecture are minimized, and existing vector instructions are used wherever possible. A similar approach is applied in the RV64X project, which also develops an open GPU based on RISC-V technologies. <\/p>\n
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For graphics, the open GPU Skybox is being developed on Vortex technologies, supporting the Vulkan graphics API. The Skybox prototype, created on the Altera Stratix 10 FPGA and including 32 cores (512 threads), achieved a fill rate of 3.7 gigapixels per second (29.4 gigatransactions per second) at a frequency of 230 MHz. It is noted that this is the first open GPU with both software and hardware implementation supporting Vulkan. <\/p>\n
Key features of Vortex: <\/p>\n
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Support for 32-bit and 64-bit RISC-V instruction set architectures RV32IMF and RV64IMAFD. <\/li>\n
Customizable number of cores, task blocks (warps), and threads.\n
Customizable number of ALUs, FPUs, LSUs, and SFUs for each core.\n
Customizable pipeline issue width.\n
Optional shared memory and caches at levels L1, L2, and L3.\n
Support for OpenCL 1.2 specification.\n
Ability to implement on Altera Arria 10, Altera Stratix 10, Xilinx Alveo U50, U250, U280, and Xilinx Versal VCK5000 FPGA.\n
Advanced instructions: for faster texture processing, vx_rast for rasterization control, vx_rop for fragment processing, depth and transparency, vx_imadd for performing the \"multiply and add\" operation, vx_wspawn, vx_tmc and vx_bar for activating instruction fronts and the threads within them (wavefront, thread group, simultaneously executed SIMD Engine), vx_split and vx_join.\n
Support for intermediate shader representation SPIR-V is implemented through translation to OpenCL.\n
For application development, a toolkit is offered, including adapted versions of PoCL (OpenCL compiler and runtime), LLVM\/Clang, GCC, and Binutils for working with Vortex.\n
Chip operation simulation is supported using Verilator (Verilog simulator), RTLSIM (RTL simulation), and SimX (software simulation). <\/ul>\n
Changes in version Vortex 2.0 include: <\/p>\n
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Microarchitecture optimizations have been conducted.\n
Support for the 64-bit RISC-V instruction set architecture RV64IMAFD has been added.\n
The ability to implement on Xilinx FPGA has been added.\n
Support for LLVM 16 and Ubuntu 20.04 has been added.\n
Refactoring has been carried out, and fixes have been made for issues identified during quality assessment. <\/ul>\n
![\"Vortex](\"\/wp-content\/uploads\/2023\/11\/200fcfdbad5e085ae5e1b154b75b1210.png\")
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