{"id":111676,"date":"2023-11-21T15:10:42","date_gmt":"2023-11-21T13:10:42","guid":{"rendered":"https:\/\/prohoster.info\/blog\/novosti-interneta\/vypusk-gipervizora-xen-4-18"},"modified":"2023-11-21T15:10:42","modified_gmt":"2023-11-21T13:10:42","slug":"vypusk-gipervizora-xen-4-18","status":"publish","type":"post","link":"https:\/\/prohoster.info\/en\/blog\/news\/vypusk-gipervizora-xen-4-18","title":{"rendered":"Release of Xen hypervisor 4.18","gt_translate_keys":[{"key":"rendered","format":"text"}]},"content":{"rendered":"
After 11 months of development, the release of the free hypervisor Xen 4.18 has been published. Companies such as Amazon, Arm, Bitdefender, Citrix, EPAM Systems, and AMD participated in the development of the new release. Updates for the Xen 4.18 branch will continue until May 16, 2025, while the publication of vulnerability fixes will last until November 16, 2026. <\/p>\n
Key changes in Xen 4.18: <\/p>\n
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Initial implementations of ports for RISC-V and Power (ppc64le) architectures have been added. Testing environments for RISC-V and Power ports are set up in the GitLab CI continuous integration system.\n
When operating on ARM64 systems, the memory subsystem of Xen has taken into account the features of the ARM architecture. Experimental support for SVE (Scalable Vector Extension) vector instructions has been added. The Arm Firmware Framework tools have been included for ARM A-profile architecture (ARM Application-profile, FF-A). An experimental feature for dynamically adding and removing nodes in the Xen device tree using .dtbo files has been introduced.\n
On Intel-based systems, the MSR_ARCH_CAPS parameter is now visible in guest systems and can be configured through the virtual machine configuration file. On processors released since 2019, the MSR_ARCH_CAPS parameter reveals what hardware fixes are applied to vulnerabilities related to speculative execution of operations.\n
Support for the CPUID_USER_DIS (CPUID Faulting) extension has been added, introduced in the fourth generation of AMD EPYC processors to control the ability to view CPUID data from the paravirtualized guest system.\n
Support for extensions introduced in Intel processors based on the Sapphire Rapids microarchitecture has been added:\n
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For guest systems in HVM and PVH modes, support for the PKS (Protection Key Supervisor) mechanism has been added, enhancing memory page protection capabilities.\n
To prevent the entire system from crashing due to issues with microarchitectural locking, the VM-Notify mechanism has been implemented.\n
Protection against bus locking due to unintended use of atomic instructions in the guest system has been added (rate-limit enabled). <\/ul>\n
Support for AVX512-FP16 instructions, which appeared in Intel CPUs based on the Granite Rapids microarchitecture, has been introduced.\n
A cpufreq driver has been added, utilizing the HWP (Hardware P-States) mechanism for managing power consumption and frequency in Intel processors.\n
Support for enforced execution of system operations in DOITM (Data Operand Independent Timing Mode) has been implemented, ensuring constant execution time of instructions regardless of the data processed by these instructions.\n
The implementation of requirements for developing safe and reliable programs in C, as outlined in the MISRA-C specifications for safety-critical systems, has continued. The number of MISRA-C directives implemented in Xen has increased from 4 to 6, while the rules have expanded from 24 to 65 (the specification contains a total of 16 directives and 143 rules).\n
The xl\/libxl toolset now provides the ability to change SMBIOS settings for guest systems in HVM mode.\n
Two new hypercalls have been added to bind the operational state and temporal areas of vCPUs to physical rather than virtual addresses. <\/ul>\n