{"id":114645,"date":"2024-03-29T12:25:42","date_gmt":"2024-03-29T10:25:43","guid":{"rendered":"https:\/\/prohoster.info\/blog\/novosti-interneta\/proekt-furygpu-razvivaet-gpu-na-baze-fpga"},"modified":"2024-03-29T12:25:42","modified_gmt":"2024-03-29T10:25:43","slug":"proekt-furygpu-razvivaet-gpu-na-baze-fpga","status":"publish","type":"post","link":"https:\/\/prohoster.info\/en\/blog\/news\/proekt-furygpu-razvivaet-gpu-na-baze-fpga","title":{"rendered":"The FuryGpu project develops a GPU based on FPGA.","gt_translate_keys":[{"key":"rendered","format":"text"}]},"content":{"rendered":"<p>A working prototype of the FuryGpu project has been presented, developing a custom GPU based on the Xilinx Zynq UltraScale+ FPGA, designed as a separate board that connects to a PC via a PCIe interface. Hardware block descriptions are implemented in SystemVerilog, and the board design is prepared in the free PCB design software KiCAD. In its current state, the FuryGpu GPU already allows running the game Quake with a rendering performance of 60 FPS at a resolution of 1280 x 720.     <\/p>\n<p>The project has been under development since 2021 as a hobby by a programmer specializing in computer game development and interested in hardware. The board schematics, Verilog descriptions, and drivers are currently not publicly available, but the project author has stated intentions to release all related FuryGpu developments after agreeing on some legal matters with their employer (the agreement is necessary to protect against potential claims from the employer).     <center><img decoding=\"async\" alt=\"The FuryGpu project develops a GPU based on FPGA.\" src=\"\/wp-content\/uploads\/2024\/03\/02cc2c1f50d250f791abdc3c009294f9.jpg\" style=\"display:block;margin: 0 auto;\" \/><\/center>    <\/p>\n<p>At its current stage of development, the capabilities of FuryGpu are comparable to an advanced graphics card from the mid-1990s. The GPU's functionality is defined by a set of fixed functions; support for programmable shaders is not yet available, and the main focus is on components for rendering, rasterization, and texture processing. For performing graphical operations, there is a dedicated graphics API called FuryGL, resembling the Vulkan API but incompatible with it due to the lack of shader support.    <\/p>\n<p>Among the already available features are:   <\/p>\n<ul>\n<li class=\"l\"> Four independent tile rasterizers;\n<li class=\"l\"> GPU operation at 400MHz, texture control block operation at 480MHz;\n<li class=\"l\"> Frontend for performing floating-point operations (fp32);\n<li class=\"l\"> A texture mapping and processing block supporting linear and bilinear filtering with MIP texturing support;\n<li class=\"l\"> PCIe Gen 2\u00d74 interface. Availability of DisplayPort and HDMI ports for monitor connection.    <\/ul>\n<p>  <center><img decoding=\"async\" alt=\"The FuryGpu project develops a GPU based on FPGA.\" src=\"\/wp-content\/uploads\/2024\/03\/4e86bd5fe5adff03637c135e6bee30bc.png\" style=\"display:block;margin: 0 auto;\" \/><\/center><br \/>\n<br \/>Source: <a content=\"nofollow\" rel=\"nofollow\" href=\"https:\/\/www.opennet.ru\/opennews\/art.shtml?num=60873\">opennet.ru<\/a> <\/p>","protected":false,"gt_translate_keys":[{"key":"rendered","format":"html"}]},"excerpt":{"rendered":"<p>\u041f\u0440\u0435\u0434\u0441\u0442\u0430\u0432\u043b\u0435\u043d \u0440\u0430\u0431\u043e\u0447\u0438\u0439 \u043f\u0440\u043e\u0442\u043e\u0442\u0438\u043f \u043f\u0440\u043e\u0435\u043a\u0442\u0430 FuryGpu, \u0440\u0430\u0437\u0432\u0438\u0432\u0430\u044e\u0449\u0435\u0433\u043e \u0441\u0430\u043c\u043e\u0434\u0435\u043b\u044c\u043d\u044b\u0439 GPU \u043d\u0430 \u043e\u0441\u043d\u043e\u0432\u0435 FPGA Xilinx Zynq UltraScale+, \u043e\u0444\u043e\u0440\u043c\u043b\u0435\u043d\u043d\u044b\u0439 \u0432 \u0432\u0438\u0434\u0435 \u043e\u0442\u0434\u0435\u043b\u044c\u043d\u043e\u0439 \u043f\u043b\u0430\u0442\u044b, \u043f\u043e\u0434\u043a\u043b\u044e\u0447\u0430\u0435\u043c\u043e\u0439 \u043a \u041f\u041a \u0447\u0435\u0440\u0435\u0437 \u0438\u043d\u0442\u0435\u0440\u0444\u0435\u0439\u0441 PCIe. \u041e\u043f\u0438\u0441\u0430\u043d\u0438\u044f \u0430\u043f\u043f\u0430\u0440\u0430\u0442\u043d\u044b\u0445 \u0431\u043b\u043e\u043a\u043e\u0432 \u0440\u0435\u0430\u043b\u0438\u0437\u043e\u0432\u0430\u043d\u044b \u043d\u0430 \u044f\u0437\u044b\u043a\u0435 SystemVerilog, \u0430 \u043f\u0440\u043e\u0435\u043a\u0442 \u043f\u043b\u0430\u0442\u044b \u043f\u043e\u0434\u0433\u043e\u0442\u043e\u0432\u043b\u0435\u043d \u0432 \u0441\u0432\u043e\u0431\u043e\u0434\u043d\u043e\u0439 \u0441\u0438\u0441\u0442\u0435\u043c\u0435 \u0430\u0432\u0442\u043e\u043c\u0430\u0442\u0438\u0437\u0438\u0440\u043e\u0432\u0430\u043d\u043d\u043e\u0433\u043e \u043f\u0440\u043e\u0435\u043a\u0442\u0438\u0440\u043e\u0432\u0430\u043d\u0438\u044f \u043f\u0435\u0447\u0430\u0442\u043d\u044b\u0445 \u043f\u043b\u0430\u0442 KiCAD. \u0412 \u0442\u0435\u043a\u0443\u0449\u0435\u043c \u0432\u0438\u0434\u0435 GPU FuryGpu \u0443\u0436\u0435 \u043f\u043e\u0437\u0432\u043e\u043b\u044f\u0435\u0442 \u0437\u0430\u043f\u0443\u0441\u0442\u0438\u0442\u044c \u0438\u0433\u0440\u0443 Quake \u0441 [&hellip;]<\/p>\n","protected":false,"gt_translate_keys":[{"key":"rendered","format":"html"}]},"author":1,"featured_media":114646,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[702],"tags":[],"class_list":["post-114645","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-news"],"aioseo_notices":[],"aioseo_head":"\n\t\t<!-- All in One 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