{"id":119157,"date":"2024-08-07T15:43:09","date_gmt":"2024-08-07T13:43:10","guid":{"rendered":"https:\/\/prohoster.info\/blog\/novosti-interneta\/dostupen-vortex-2-2-otkrytyj-gpgpu-na-baze-arhitektury-risc-v"},"modified":"2024-08-07T15:43:09","modified_gmt":"2024-08-07T13:43:10","slug":"dostupen-vortex-2-2-otkrytyj-gpgpu-na-baze-arhitektury-risc-v","status":"publish","type":"post","link":"https:\/\/prohoster.info\/en\/blog\/news\/dostupen-vortex-2-2-otkrytyj-gpgpu-na-baze-arhitektury-risc-v","title":{"rendered":"Vortex 2.2 is available, an open GPGPU based on RISC-V architecture","gt_translate_keys":[{"key":"rendered","format":"text"}]},"content":{"rendered":"

The release of the Vortex 2.2 project has been published, which develops an open GPGPU based on the RISC-V instruction set architecture, aimed at performing parallel computations using the OpenCL API and the SIMT (Single Instruction, Multiple Threads) execution model. The project can also be used for research in the field of 3D graphics and for developing new GPU architectures. Schematics, hardware block descriptions in Verilog, a simulator, drivers, and accompanying project documentation are distributed under the Apache 2.0 license. <\/p>\n

The foundation of GPGPU is based on the standard RISC-V ISA, extended with some additional instructions necessary for supporting GPU features and managing threads. Changes to the RISC-V architecture instruction set are minimized, utilizing existing vector instructions whenever possible. Among the additional instructions are: «tex» for accelerating texture processing, vx_rast for controlling rasterization, vx_rop for fragment processing, depth, and transparency, vx_imadd for performing the «multiply and add» operation, vx_wspawn, vx_tmc, and vx_bar for activating instruction fronts and the threads within them (wavefront, a set of threads executed in parallel by the SIMD Engine), vx_split and vx_join.

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The developed GPGPU supports 32- and 64-bit RISC-V RV32IMF and RV64IMAFD instruction set architectures and may include optional shared memory, L1, L2, and L3 caches, as well as a customizable number of cores, warps, and threads. Each core is designed to allow a configurable number of ALU, FPU, LSU, and SFU. Prototypes can utilize Altera Arria 10 FPGA, Altera Stratix 10, Xilinx Alveo U50, U250, U280, and Xilinx Versal VCK5000. For simulating chip operation, Verilator (Verilog simulator), RTLSIM (RTL simulation), and SimX (software simulation) may be used. <\/p>\n

The development of applications is supported by a toolkit that includes Vortex-adapted versions of PoCL (OpenCL compiler and runtime), LLVM\/Clang, GCC, and Binutils. The project supports the OpenCL 1.2 specification and has implemented support for the SPIR-V intermediate representation of shaders via translation to OpenCL. For graphics on Vortex technologies, an open GPU Skybox is being developed, supporting the Vulkan graphics API. The Skybox prototype, built on the Altera Stratix 10 FPGA and featuring 32 cores (512 threads), achieved a fill rate of 3.7 gigapixels per second (29.4 gigatransactions per second) at a clock speed of 230 MHz. <\/p>\n

Among the changes in version Vortex 2.2: <\/p>\n