{"id":120495,"date":"2024-11-05T13:09:14","date_gmt":"2024-11-05T11:09:15","guid":{"rendered":"https:\/\/prohoster.info\/blog\/novosti-interneta\/ispolzovanie-v-ffmpeg-instrukczij-avx-512-pozvolilo-v-94-raza-uskorit-nekotorye-operaczii"},"modified":"2024-11-05T13:09:14","modified_gmt":"2024-11-05T11:09:15","slug":"ispolzovanie-v-ffmpeg-instrukczij-avx-512-pozvolilo-v-94-raza-uskorit-nekotorye-operaczii","status":"publish","type":"post","link":"https:\/\/prohoster.info\/en\/blog\/news\/ispolzovanie-v-ffmpeg-instrukczij-avx-512-pozvolilo-v-94-raza-uskorit-nekotorye-operaczii","title":{"rendered":"The use of AVX-512 instructions in FFmpeg has accelerated some operations by 94 times.","gt_translate_keys":[{"key":"rendered","format":"text"}]},"content":{"rendered":"

The developers of the FFmpeg project have announced the implementation of new assembly optimizations that, thanks to the use of AVX-512 instruction sets, have accelerated certain operations used in video decoding. The performance gain of the assembly code utilizing AVX-512 instructions was 94, 44, 64, and 4.24 times compared to the baseline implementation written in C without the use of SIMD instructions. In the assembly code optimized with AVX-2 instructions, the gains were 67, 27, 55, and 4.38 times respectively, while with SSSE3 instructions, the gains were 40, 21, 29, and 2.49 times. These changes have been incorporated into the dav1d library, which offers an alternative decoder for the AV1 video encoding format. AVX-512 instructions are available in AMD processors based on Zen 4 and 5 microarchitectures, as well as in Intel processors based on microarchitectures such as Skylake-X, Ice Lake, Tiger Lake, and Rocket Lake.

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Source: opennet.ru<\/a> <\/p>","protected":false,"gt_translate_keys":[{"key":"rendered","format":"html"}]},"excerpt":{"rendered":"

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