{"id":184097,"date":"2026-11-02T23:40:40","date_gmt":"2026-11-02T21:40:40","guid":{"rendered":"https:\/\/prohoster.info\/blog\/news\/vypusk-svt-av1-4-3-0-kodirovshhika-dlya-formata-video-av1"},"modified":"2026-11-02T23:40:47","modified_gmt":"2026-11-02T21:40:47","slug":"svt-av1-4-3-0-av1-video-encoder-released","status":"publish","type":"post","link":"https:\/\/prohoster.info\/en\/blog\/news\/svt-av1-4-3-0-av1-video-encoder-released","title":{"rendered":"Release of SVT-AV1 4.3.0, an encoder for the AV1 video format","gt_translate_keys":[{"key":"rendered","format":"text"}]},"content":{"rendered":"
The release of the SVT-AV1 4.3.0 library (Scalable Video Technology AV1) has been published, featuring implementations of both the encoder and decoder for the AV1 video coding format, utilizing the hardware parallelism capabilities present in x86_64 and ARM processors. This project was created by Intel in partnership with Netflix to achieve a performance level suitable for on-the-fly video transcoding and for use in video on demand (VOD) services. Currently, development is being carried out under the auspices of the Alliance for Open Media (AOMedia), which oversees the development of the AV1 video coding format. Previously, the project developed within the OpenVisualCloud initiative, which also develops the SVT-HEVC and SVT-VP9 encoders. The code is distributed under the BSD license. <\/p>\n
SVT-AV1 can be built for systems based on any architecture that has a compiler supporting the C99 standard, but the best performance is achieved on x86_64 systems, where assembler optimizations based on SIMD instructions are applied (AVX2 support in the CPU is preferred, but SSE2 is sufficient as a minimum). Memory consumption depends on the number of CPU cores used during encoding, which is controlled by the option «—lp». Due to the complexity of the algorithms used in AV1, encoding this format requires significantly more resources than other formats. <\/p>\n
Among the changes in the new SVT-AV1 release:<\/p>\n
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Optimizations have been made for the quality\/speed trade-offs for all presets, allowing for a 5-8% reduction in CPU load while maintaining the same quality level, as well as a 10-11% reduction in encoding time in multithreaded mode. The execution of operations for excluding inefficient encoding modes (MD — Mode Decision), calculating motion vectors (MV — Motion Vector), and filter parameters during encoding, computing the size of frequency coefficients, searching for subpixel offsets, copying blocks and eliminating unnecessary detailing using the RDOQ (Rate-Distortion Optimized Quantization) algorithm has been accelerated. In multithreaded mode, to save resources, the algorithm for detecting screen content translation now applies only to I-frames.\n
An experimental flag «—fast-decode 3» has been added to speed up the decoding of static images.\n
A flag «—fgs-table» has been added, enabling support for film grain tables, and the API FILM_GRAIN_EVENT for setting grain parameters in relation to frames.\n
The speed of lossless encoding has been improved.\n
In low-latency encoding mode, parallel processing of tile blocks has been implemented.\n
An option «max_allowed_consecutive_frames_skips» has been added to configure frame skipping in constant bitrate (CBR) mode.\n
A parameter «max_hierarchical_levels» has been added to control the buffer pool used when resizing groups of intermediate frames (mini-GOP — Group of Pictures).\n
A build option «—mobile-build» (in CMake — MOBILE_BUILD) has been added to create an 8-bit library for RTC, VOD, and AVIF. Options CONFIG_ENABLE_* have been added to disable the building of unused encoding tools.\n
For x86 systems, 8-bit CDEF handlers based on AVX2 and SSE4.1 instructions, as well as 16-bit direct transformations based on AVX2 and AVX-512 instructions, have been implemented. Optimized code using SSE4.1 instructions has been added for inter-frame prediction, palette handling, and transformations. Handlers for quantization, block copying, distortion calculation, and subpixel difference evaluation have been optimized.\n
For ARM systems, processor-instruction accelerated handler variants using Neon have been added.\n<\/ul>\n